Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • Creating an Optimal Safety Architecture  - February 9th
      • The ABC of Formal Verification - February 11th
      • Events Calendar
    • On Demand Seminars

      • I'm Excited About Formal...
      • Visualizer Coverage
      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • All On-Demand Seminars
    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings
    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training
    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us
    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
Ask a Question
UVM analysis port
  • Home
  • Forums
  • UVM
  • Forums: UVM

Forums: UVM

Primary tabs

  • Active
  • Solutions
  • Replies
  • No Replies
  • All(active tab)

15 questions in UVM

  • TITLE
    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • Connecting Sequence to Scoreboard
    6  
    461  
    5 months 3 weeks ago
    by om30  
    5 months 2 weeks ago
    by hungvn  
  • Monitor scoreboard Error
    4  
    301  
    10 months 3 weeks ago
    by UVM_SV_101  
    10 months 2 weeks ago
    by chr_sue  
  • Usage of pair_ap from uvm_in_order_comparator
    2  
    434  
    1 year 5 months ago
    by Jose_Iuri  
    1 year 5 months ago
    by Jose_Iuri  
  • UVM_DRIVER- Driving an interface at an event.
    1  
    751  
    1 year 10 months ago
    by Pooja Pathak  
    1 year 10 months ago
    by chr_sue  
  • Overhead of calling analysis port write() method
    2  
    916  
    2 years 5 months ago
    by Omkar  
    2 years 5 months ago
    by Omkar  
  • where to use ports and analysis ports
    6  
    452  
    2 years 6 months ago
    by sreekanth reddy undi  
    2 years 5 months ago
    by chr_sue  
  • Getting same item from analysis fifo, even though monitor writes only once
    4  
    949  
    2 years 10 months ago
    by saravanantvs  
    2 years 10 months ago
    by dave_59  
  • Whats the difference between hierarchical exports direct assignment and hierarchical exports assign through connect?
    1  
    706  
    3 years 3 weeks ago
    by Mayur Chaudhari  
    3 years 3 weeks ago
    by sharvil111  
  • Configuring driver-sequencer used, from environment?
    5  
    1,039  
    3 years 8 months ago
    by smukerji  
    3 years 8 months ago
    by chr_sue  
  • Can I have an analysis port inside my driver ?If yes, then why we have monitor ?If no,why ?
    3  
    1,946  
    4 years 5 months ago
    by utkalikapanda  
    4 years 4 months ago
    by utkalikapanda  
  • If I do not connect uvm_analysis_port to uvm_analysis_imp and use uvm_analysis_port.write method. What should happen
    3  
    1,128  
    5 years 5 days ago
    by JDS  
    5 years 2 days ago
    by dave_59  
  • UVM analysis port
    3  
    1,229  
    5 years 1 month ago
    by ashutosh1122  
    5 years 1 month ago
    by kk@007  
  • About the analysis port "write" function implementation
    2  
    4,170  
    5 years 9 months ago
    by anu.anu  
    5 years 9 months ago
    by Ashith  
  • Failing to connect analysis port.
    4  
    1,332  
    6 years 9 months ago
    by adlsdk  
    6 years 9 months ago
    by yaohe  
  • Can we use ports in driver, inside driver callback method driver's handle?
    7  
    2,050  
    6 years 10 months ago
    by dipali  
    6 years 10 months ago
    by dipali  

13,469 Questions

40,356 Replies

69,376 Users

Welcome to the Verification Academy Forums.

The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions.

We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

Important Links

  • Ask a Question
  • Use Code Tags
  • Forum FAQ
  • Forum Search
  • Forum Subscriptions

Forum Reminders

Do NOT begin your question with a "dot" (.do script).
Do NOT ask single word questions. Be specific!
Do NOT ask tool questions. Contact your tool vendor directly for support!


To help prevent Forum spam, your first question asked will be moderated.

Subscribe to Forums: UVM

Available Forums

  • UVM
  • OVM
  • SystemVerilog
  • Coverage
  • Downloads
  • Announcements

Forum Tags

  • #uvm 238
  • UVM 141
  • uvm 124
  • #systemverilog 76
  • RAL 52
  • #UVM #RAL 51
  • uvm_config_db 37
  • uvm_reg 26
show all tags
Ask a Question
Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 498 5351

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy