In reply to pk_94:
People sometime use the word "static" to mean an object that gets created at time 0 and exists for the entire simulation. It is not "static" in the official SystemVerilog keyword sense. I prefer to use the term "structural" or "topological" for uvm_component objects rather than confuse people with "static"
The factory can be used by any class derived from uvm_object.
Also, uvm_object is a base class, not a parent class of uvm_component. Do not use the terms parent/child when dealing with inheritance. You always construct just one object, and that object inherits all the properties down to the base class.