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  • All uvm_components extended from uvm_object at the end in the uvm_hierarchy , then how uvm_object is different from uvm_component ?

All uvm_components extended from uvm_object at the end in the uvm_hierarchy , then how uvm_object is different from uvm_component ?

UVM 5686
uvm_component hierarchy 2 uvm_component 8 uvm_object 8 #uvm 251
pk_94
pk_94
Full Access
74 posts
October 22, 2018 at 12:06 am

As we know uvm_components are static in nature and are build during build phase while uvm_object (like uvm_trasaction) are non static ,meaning they can be changed during run time.One more thing is that factory creation is not possible in uvm_object unlike uvm_component. But the question is all the uvm_components are derived from uvm_object in the uvm hierarchy ,so how its possible in anyway , or am I missing something ? Is the uvm_object mentioned in the uvm hierarchy is misnomer. Please explain.

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chr_sue
chr_sue
Full Access
3328 posts
October 22, 2018 at 12:30 am

In reply to pk_94:

See in the UVM Reference Manual.

class uvm_component extends uvm_report_object;
class uvm_report_object extends uvm_object;

In general for uvm_component reporting capbilities are added to the uvm_object class.

pk_94
pk_94
Full Access
74 posts
October 22, 2018 at 12:55 am

In reply to chr_sue:

Thats true, but uvm_component is a child and uvm_object is a parent ), then how can we say that uvm_component being a child is static in nature while the uvm_object being the parent is dynamic in nature ,it is possible ?

Solution

Solution

dave_59
dave_59
Forum Moderator
8757 posts
October 22, 2018 at 10:01 am

In reply to pk_94:
People sometime use the word "static" to mean an object that gets created at time 0 and exists for the entire simulation. It is not "static" in the official SystemVerilog keyword sense. I prefer to use the term "structural" or "topological" for uvm_component objects rather than confuse people with "static"
The factory can be used by any class derived from uvm_object.

Also, uvm_object is a base class, not a parent class of uvm_component. Do not use the terms parent/child when dealing with inheritance. You always construct just one object, and that object inherits all the properties down to the base class.

— Dave Rich, Verification Architect, Siemens EDA

pk_94
pk_94
Full Access
74 posts
October 23, 2018 at 12:46 am

In reply to dave_59:

Thanks for the clarification Dave.Just one more thing is ,why parent/child is not preferred when dealing with inheritance ? Is there any issue in using that terminology ?

dave_59
dave_59
Forum Moderator
8757 posts
October 23, 2018 at 7:18 am

In reply to pk_94:
Parents create(construct) children and they are distinct objects from their parents. When you inherit property, that property becomes yours and all your property belongs to one object. Use base and extended.

The UVM uses terms parent and child to refer to relationships between objects when building a hierarchical tree/graph structure. The class uvm_component has a handle to its parent and handles to all its children so that you can traverse the hierarchical structure. This terminology is used in most programming languages and is independent of OOP.

— Dave Rich, Verification Architect, Siemens EDA

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