All changes in a signal driven from seq is not reflected on interface but only last value is seen

Hi,

I have a sequence inside which i call a tasks multiple times. In the task i toggle clk signal. In results i see only the last change in the clk signal but not all the toggles.

Is there any solution to see each change in the clk signal on the interface ?

run phase of driver:

task run_phase (uvm_phase phase);
		forever begin
			seq_item_port.get_next_item(req);
			drive(req); //assign req to virtual interface
			seq_item_port.item_done();
		end
	endtask : run_phase

sequence body task:

	task body();
		my_seq_item req;
		req = my_seq_item::type_id::create("req");
	        start_item(req);
		  write_data(req, 1, 0);
	          write_data(req, 2, 1);
 		finish_item(req);
			

tasks file:

task write_data(seq_item req, addr, data);
   req.clk =0;
   req.clk=1;
   req.clk=0;
   req.clk=1;
   req.addr=addr;
   req.data=data;
endtask

In reply to v.siri:

I believ you have awrong understanding of the seq_item generation in the body task.
The body task is generating a series of seq_items for further processing in the driver.
Please note the body task of the sequence does not know anything about timimg and clock cycles.
It seems your seq_item has a data member clk. Looks like you are considering this as your clock.

req.clk =0;
req.clk=1;
req.clk=0;
req.clk=1;

is useless because you are overriding the clk data member 3 times because there is not progress in time in between.
With the code

start_item(req);
write_data(req, 1, 0);
write_data(req, 2, 1);
finish_item(req);

You are overriding the first write_data by the 2nd one. There is also no progres in time in between.
You should replace this piece of code with

start_item(req);
write_data(req, 1, 0);
finish_item(req);
start_item(req);
write_data(req, 2, 1);
finish_item(req);

Hi,

Thankyou for the quick response.
Actually i would like to include delays in the write_data task:

req.clk =0;
#50ns
req.clk=1;
#50ns
req.clk=0;
#50ns
req.clk=1;

and also in sequence:
start_item(req);
write_data(req, 1, 0);
finish_item(req);
#500ns
start_item(req);
write_data(req, 2, 1);
finish_item(req);

i would expect a output where clk toggles and then addr, data is written. after 500ns the clk should toggle again with new adddr and data.
But this does not happen. the clk remains at the last value

In reply to v.siri:
What you are doing is useless. The sequencer works on the Transaction Level. It dies not know anything about timing and clock cycles. Any timing will be implemented in the driver.
You are getting a sequence item from the sequencer containing data for addr and data. In the toplevel module you have to implment a clcok generator and passing the clock signal to the driver (using the virtual interface and the config_db.