Address Overlap Issue using Questa Register Assistant Feature

UVM
, , ,
1

Hi All,

I am using Questa’s Register Assistant feature to generate my RAL model from predefined CSV formats. I have 2 16bit wide registers named regA and regB. The address is of 32 bit where each nibble signifies some particular feature about that register. The address of register regA is 0x00000000 and that of register regB is 0x00000001. The address have been specified in the registers.csv and maps.csv file. But I am getting an error like this:

Error: Address Overlap detected in Address Map ‘bus_map’.

Error: - Overlap between Register Instance regA[addressOffset=0x00000000, Definition=regA, dimension=0, resetValue=null] and Register Instance regB[addressOffset=0x00000001, Definition=regB, dimension=0, resetValue=null]

Can anyone help me with this?

2

In reply to atanu.biswas:

You are expecting word addressing A@0, B@1, but it looks like your tool is expecting byte addressing A@0, B@2. Byte addressing is also the default scheme used by uvm_reg. Your tool should be able to control which addressing scheme is being used, so you should contact your vendor for support with that.

However, regardless of which tool you use to generate a reg model, or whether you build your model by hand, the address scheme is controlled by the byte_addressing parameter to the uvm_reg_map::configure function, which defaults to 1.


// From class uvm_reg_map
function void configure(
   		uvm_reg_block 	 parent,	  	
   		uvm_reg_addr_t 	 base_addr,	  	
   	int 	unsigned         n_bytes,	  	
   		uvm_endianness_e endian,	  	
   		bit              byte_addressing = 1
)
3

In reply to warnerrs:

So is there any particular field in the CSV formats for specifying word addressing?

4

In reply to atanu.biswas:

¯_(ツ)_/¯

The CSV format is tool specific, please contact your tool vendor.