I am wondering if anyone out there has a sophisticated available for learning purposes.
I am writing a test bench for a cache controller for a superscalar processor. I’d like to
see how people handle address generation or similar things. I need to get addresses from
utlb entries that I generate at time zero. also I set up a memory slave in a uvm_component
that I can reference by saving a pointer to it in the config_db. only catch is I can’t
get the pointer from the uvm_config_db from inside the sequence, but I can get it from
inside the driver.
What is the best way to do address generation in the sequencer (getting addresses from a uvm_component
that manages UTLB entries and addresses in the memory slave? For load addresses I need to use addresses
that are available in my memory slave.