Adding hdl path UVM RAL

UVM
1

In the uvm_reg method

 add_hdl_path_slice(string name,	  	
   	int 	offset,	  	
   	int 	size,	  	
   	bit 	first	 = 	0,
   	string 	kind	 = 	"RTL")

is the string name the name of the register field or is it the name of the RTL counterpart?

For example, say I have a 32 bit register X with a_x,b_x,c_x fields that occupy certain bits of the register. [ X[3] = a_x, X[5] = b_x, X[31] = c_x] These fields have corresponding flops (a,b,c) on the rtl and the other bits are unused. How is the hdl path added for such a case?


//In X reg file build function
a_x.configure(this, 1, 3);
b_x.configure(this, 1, 5);
c_x.configure(this, 1, 31);
add_hdl_path_slice("", 3, 1);  //for a_x would the string name be a_x or a?

for a_x would the string name be a_x or a?

2

In reply to Vaishnavi Balasubramanian:

Hello, the string name is the path up to the register instance in the RTL something like:


   uut.i1.i2.i3.register

In your case that path to the field doesn’t exist in the RTL meaning sometimes RTL uses DEFINES to make it clearer what bit of a specific field is deployed. Names provided in the RAL model are just result of the register description used.

the path will be:


//In X reg file build function
a_x.configure(this, 1, 3);
b_x.configure(this, 1, 5);
c_x.configure(this, 1, 31);
add_hdl_path_slice("uut.i1.i2.i3.4.regsiter_name", 3, 1);  //for a_x would the string name be a_x or a?

in case you wanna ad a bit specific path you would need to use:


$sformatf("uut.i1.i2.i3.4.regsiter_name[%0d]",bit_sel)

// or a define

`define reg_a_bit_sel(sel) $sformatf("uut.i1.i2.i3.4.regsiter_name[%0d]",``sel``)

Regards