Adding additional ports to driver/sequencer pair

Hi,
The uvm_sequencer/driver pair is connected through, seq_item_port and seq_item_export. Can we add another port/export pair in a sequencer/driver pair. Below the conceptual pseudo code. Now if we have a sequence that runs on this sequencer, would it be able to drive two sets of mutually exclusive signals, of the same interface through this sequencer driver pair? One using the existing seq_item_port and the other using my_seq_port?
Thanks,
Anshu

class my_sequencer extends uvm_sequencer;

uvm_seq_item_pull_imp #(
   	REQ,
   	RSP,
   	this_type
) my_export

endclass

class my_driver extends uvm_sequencer;

uvm_seq_item_pull_port #(REQ, RSP) my_seq_port;

run_phase()
fork
begin
get_next_item(req)

finish_item
end

begin
my_seq_port.get_next_item(req1)

finish_item
end
endclass
my_sequencer.my_export.connect(my_driver.my_seq_port;

In reply to anshushr:

Maybe. See TLMs between sequencer and driver? | Verification Academy