I am looking for solution to abstract sequence that implements algorithm from final bus agent. Bus can be different for sub block and top level.
One approach that i am in process to implement will be create adapter agent that perform following:
1. Gets items of generic sequence.
2. Create item for current agent that used in test bench.
3. Sends item to sequencer of this agent.
Is there better way to avoid this layer, something similar as uvm_reg_adapter that available for register model.