Adapter for abstracting sequence from final driver

UVM
1

Hi,
I am looking for solution to abstract sequence that implements algorithm from final bus agent. Bus can be different for sub block and top level.
One approach that i am in process to implement will be create adapter agent that perform following:

  1. Gets items of generic sequence.
  2. Create item for current agent that used in test bench.
  3. Sends item to sequencer of this agent.
    Is there better way to avoid this layer, something similar as uvm_reg_adapter that available for register model.

Thanks,

2

In reply to albert.waissman@intel.com:
What do you mean with ‘sequence that implements algorithm from final bus agent’.
A sequence generates seq_items that contain data used for an algorithm.

3

In reply to albert.waissman@intel.com:

I don’t know exactly what’s in your sequence, but it boils down to… the definition of your transactions should already by abstracted from a specific interface. So at block, subsystem, or top SoC level, your transaction class is the same. The bus specific intelligence lies in the driver and/or interface. Some more details of your sequence would probably help tho…

4

In reply to bmorris:
Thanks for reply.
My generic sequence basically generates items that contain address, data and command that needs to be send to HW. This HW can be configured with different interface AXI or PCIe.
From test I will start this sequence on some sequencer, and my expectation that some where those items will go through some kind of adapter that will create item for agent that installed in environment (AXI or PCIe) and start this item on sequencer of the agent. I am looking for something similar to register layer adapter concept. Probably I have to crate agent that will behave as adapter.
Thanks again,

5

In reply to albert.waissman@intel.com:

OK, I understand. You want to use your sequence items and the corresponding sequences for both functional interfaces (AXI, PCIe) because you are assuming they need both the same entries (address, data, command). I believe this is not a good idea, because you are creating an environment which is not flexible when you have to make modifications. I’m sure your seq_item definition will change when you are starting the simulation runs and you have to add different data fields fir AXI and PCIe. Finally you need different drivers for bot interfaces.
It is recommended to work with seperate seq_items and sequences for both interfaces.
BTW Intel has UVM environment generator which generates a complete UVM environment adopted to your needs. Please visit your intranet or contact Peter Zenk.

6

In reply to chr_sue:

Hi,
Yes I am aware of Intel proprietary layer, problem I can not use it in this project.
I got good reference for layering in UVM:
http://verificationhorizons.verificationacademy.com/volume-7_issue-3/articles/stream/layering-in-uvm_vh-v7-i3.pdf
Thanks,
Albert,

7

In reply to albert.waissman@intel.com:

layering is for protocols that have layers, like ethernet and PciE. The layering agents still hook up to a single driver. e.g. ill make a layering agent for ethernet. It will have UDP2IP agent, IP2Eth, Arp2Eth, etc. Finally, I’ll plug it into a single physical layer agent, using the techniques from the paper. btw this technique is also discussed in the cookbook.

anyway. i hope it helps you.