Hi all ,
For some reason I want to access/change the test’s ( Run from Command Line OR run_test Argument ) properties .
module top_module();
class t1 extends uvm_component;
`uvm_component_utils(t1)
uvm_blocking_put_imp #(int,t1) a1;
int BB ; // Want to Change this from top_module
function new(string name = "test",uvm_component parent = null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
a1 = new("aa1",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
endfunction
endclass
class t12 extends uvm_component;
`uvm_component_utils(t12)
uvm_blocking_put_imp #(int,t12) a12;
int BB ; // Want to Change this from top_module
function new(string name = "test",uvm_component parent = null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
a1 = new("aa1",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
endfunction
endclass
class Default_test extends uvm_test;
`uvm_component_utils(Default_test)
t1 t;
t12 r;
uvm_blocking_put_port #(int) a;
function new(string name = "Default_test",uvm_component parent = null); // Argument Names will be Overridden during create()
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
t = t1::type_id::create("t",this); // Change names to "a" , "aa"
r = t12::type_id::create("r",this);
a = new("a",this,1,2);
endfunction
function void connect_phase(uvm_phase phase);
//super.connect_phase(phase);
a.connect(t.a1); // Make Both Connections
a.connect(r.a12); // Make Both Connections
endfunction
task run_phase(uvm_phase phase);
#2 ;
endtask
endclass
initial begin
fork
run_test("Default_test");
begin
#1 ;
uvm_pkg::uvm_top.top_levels[0].t.BB = 10; // Gives an Error on 't'
end
join
end
endmodule
Any Suggestions ?