Accessing (setting in) config db from multiple initial blocks?

Currently I am putting several things in the config db from an initial block of the toplevel simulation module (mainly virtual interface abstract class handles). It would be more convenient for me if I could move some of these to another initial block of a DUT wrapper for example.

But I am doubting of this is OK, my main concerns are:

  • I am not sure if the config db will now be accessed ‘in parallel’ by the 2 initial blocks and if this ok (‘thread-safe’?)
  • One of the initial blocks has to call run_test(). I guess I need to be sure that this does not happen prior to the other initial blocks have finished?

In reply to NiLu:

I believe the UVM is littered with enough #0’s to allow any other initial block to do a uvm_config_db::set() before any phase of a uvm_component would do a ::get(). Just make sure your initial block do not contain any #0’s

As far as being thread safe, although the language is not defined with atomic execution, no existing tool uses preemptive multi-threading to implement SystemVerilog, so I would not worry about it.

In reply to dave_59:

But dealing with #0 is not a good coding style and might cause problems.

In reply to chr_sue:

In reply to dave_59:
But dealing with #0 is not a good coding style and might cause problems.

That is correct. You don’t really need to know the internals of the UVM. They could have used a wait for NBA event, which would have been more predictable and manageable. But as long as your initial block does not block before doing a set(), it will work.

In reply to dave_59:
I agree.

In reply to NiLu:

Sorry, I meant to say “does not block”. I edited my post.