Accessing RTL Submodule from TestBench Pkg

UVM
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1

Hi,

My requirement is to access RTL/DUT internal sub modules for memory backdoor access. But I am working on a project where I could not find how to access RTL from my TestBench using hierarchical approach.

Below is brief description of my TestBench and RTL block,



package test_pkg;
  // Here My TestBench/Env files are included
endpackage : test_pkg

program test;
  import test_pkg::*;

  initial begin
    run_test();
  end
endprogram : test

// Following wrapper is generated automatically through script,
// And I don't have an access of below module
module top_wrapper;
  import test_pkg::*;
  DUT dut;
  IF my_if;
  
  // From here, virtual interfaces are broadcasted using uvm_config_db using string broadcasting
  // Ex. uvm_config_db#(Virtual IF)::set(null, "VerificationAcademy", "VerificationAcademy", my_if);
  // There are many other interfaces also broadcasted into testbench using above config db
endmodule : top_wrapper

from above code, I only have an access of program block, Through program I can access DUT using $root.top_wrapper.dut.* but my requirement is to access it from my test_pkg components (ex from Scoreboard). Above program and module are compiled independently.

2

If you need to access registers via back door methods, I would recommend using the UVM register package. While this takes a little bit of extra effort, it provides built-in back door access methods so you won’t need to code them yourself.

3

In reply to cgales:

Actually, In my case there are not many registers. I need to access just single 2D Memory arrays (reg [127:0][511:0] mem8K;) which is inside in DUT. UVM RAL will be taking many more efforts and it would be preferred if there are more numbers of register residents inside DUT.

Here, I just want to access DUT 2D memory array from my test bench components (inside test_pkg), but problem is I can’t access DUT hierarchy from my test_pkt hierarchy.

4

For the solution, I have taken a debug interface inside program block and broadcasted it using uvm_config_db. Inside debug interface, I implemented read and write method by which I can directly access RTL memory module using hierarchical access. I get the virtual interface inside my test pkg using uvm_config_db::get and access write/read method from any of my testbench component.