If i want to access a variable from test to inside TB_top using hierarchical path, what would be the hierarchy please have a look at below code? please help.
Why are you trying to access information from your UVM environment in your top level testbench? The UVM is designed so that you provide any information regarding the test configuration from the top level testbench to the environment using the uvm_config_db, not the other way around.
You should follow this methodology and only pass data from the top down.
Thanks for reply,
As you suggested, we can do this using uvm_config_db.
But why I am getting error while using hierarchical path “uvm_top.uvm_test_top.count=10;”
Please let me know what is correct hierarchical path to access variable of test.
You can’t access variables in your UVM hierarchy directly because of the way the top level testbench is elaborated. At the top level, every hierarchical reference needs to be completely resolved during elaboration. Since the UVM part of the testbench is generated dynamically, there is no way to resolve it during elaboration, hence your error.
“At the top level, every hierarchical reference needs to be completely resolved during elaboration. Since the UVM part of the testbench is generated dynamically, there is no way to resolve it during elaboration, hence your error.”
With reference to above lines, If we use hierarchical path in test(env.agent.sequncer), How does it work?
Please reply.
This works because the UVM part of your testbench is class-based and dynamically created during run-time. SystemVerilog does allow hierarchical references internal to the class-based components. However, you can’t access a dynamic hierarchy (UVM classes) from the static components (RTL Testbench).