Access a variable from test to inside TB_top using hierarchical path

UVM
1

Hi All,

If i want to access a variable from test to inside TB_top using hierarchical path, what would be the hierarchy please have a look at below code? please help.

module tb_top;

initial begin

 #10ns;
 uvm_top.uvm_test_top.count=10; <-  getting error

end
.
.
.
endmodule

class base_test extends uvm_test;

int count;

endclass

Thanks,
Rahul

2

Why are you trying to access information from your UVM environment in your top level testbench? The UVM is designed so that you provide any information regarding the test configuration from the top level testbench to the environment using the uvm_config_db, not the other way around.

You should follow this methodology and only pass data from the top down.

3

I am agree with Cgales, you should pass data from top down.

I am guessing you may have different requirement where you have to perform some operation in TOPP TB if test count is equal to 10? if so you can use

  1. UVM event
  2. You can use Abstract class approach to call API from test. here is one example
    http://v4verification.com/2015/03/accessing-dut-memory-from-anywhere-in-tb-with-help-of-abstract-class/
4

In reply to Vinay Jain:

Hi,

Thanks for reply,
As you suggested, we can do this using uvm_config_db.
But why I am getting error while using hierarchical path “uvm_top.uvm_test_top.count=10;”
Please let me know what is correct hierarchical path to access variable of test.

Thanks,
Rahul Kumar

5

In reply to rahulkumarkhokher@gmail.com:

You can’t access variables in your UVM hierarchy directly because of the way the top level testbench is elaborated. At the top level, every hierarchical reference needs to be completely resolved during elaboration. Since the UVM part of the testbench is generated dynamically, there is no way to resolve it during elaboration, hence your error.

6

In reply to cgales:

Thanks cgales.

7

In reply to rahulkumarkhokher@gmail.com:

“At the top level, every hierarchical reference needs to be completely resolved during elaboration. Since the UVM part of the testbench is generated dynamically, there is no way to resolve it during elaboration, hence your error.”

With reference to above lines, If we use hierarchical path in test(env.agent.sequncer), How does it work?
Please reply.

Thanks,
Rahul Kumar

8

In reply to rahulkumarkhokher@gmail.com:

This works because the UVM part of your testbench is class-based and dynamically created during run-time. SystemVerilog does allow hierarchical references internal to the class-based components. However, you can’t access a dynamic hierarchy (UVM classes) from the static components (RTL Testbench).

9

In reply to cgales:

Thanks for explanation.