Hi all.
I am developing an I2C VIP which should update the register model of the device based on the transactions on the bus (explicit prediction).
The problem is the following: suppose the DUT has its registers organized in pages (A,B,C,…), where
Address space of A : 0x0 to 0xA
Address space of B,C (and other possible pages): all registers have addresses going from 0xB to 0x1F.
If I want to access a register in page B, first I write to register with address 0x0 (A) the number of page corresponding to B, then I can perform access (write or read) to registers contained in page B.
What is the best way to implement this behavior?
So far I’ve thought of the following options:
-
Insert in the monitor(and agent) an analysis port for each regblock (one regblock of the regmodel corresponds to a page), and keep track of the last accessed page again in the monitor, to write on the correct analysis port which leads to the correct predictor for the regblock/page.
This would mean modifying monitor and agent when de DUT changes, not so handy. -
Customize the uvm_reg_predictor class, dealing here with the specific characteristics of the register model (keep track of current page, make access only if matches with the predictor’s assigned page, etc…). Which results being bit more handy, as one doesn’t have to modify the other components every time the DUT changes, but only this class.
Have you got any suggestions or better way to implement this? Hope I was clear enough!
Thank you