Access DUT port signal in UVM Test Case

UVM
1

Hi all,

    in My UVM testbench I want to drive(access)  DUT signal  Directly    from Testcase. For this i am using $root and driving it using **"$root.top_module_name.DUT_instance_name.dut_port_signal = 1;"**  like this i wrote syntax. But it is giving some error saying that **"Ilegal Location in Hierarchical Path (in package).**  I am not able find solution for this . Can anybody help to trace this issue?

I tried in Different Ways also.
1.Tried without $root used only top_module_name.DUT_instance_name.dut_port_signal=1; this is also giving same error as above
2. Used force statement to force the port signal value like force top_module_name.DUT_instance_name.dut_port_signal=1; not working
3. tried with $unit::DUT_NAME.dut_port_signal =1 ; got an error like “SV package is not allowed to access items declared in a compilation unit scope”
4.tried with uvm_pkg::uvm_top.DUT_instance_name.dut_port_signal = 1;" this is also giving error.

Please help me if you know any thing in this regards
Thanks
balaji

2

In reply to DEGALA BALAJI:

Hi,

Directly you can use virtual interface and drive that signal from test

3

In reply to Anudeep J:

Yes you are Correct in terms of driving signals using virtual interface in Test Case. But Here the Requirement is that without using interface(the Interface which is driver only drive some set of signals(as those are containing in interface) and Remaining Signals(which are not present in Interface) i want to drive(Force) Directly from My TestCase?

4

In reply to DEGALA BALAJI:

You cannot use hierarchical paths from inside a package, because there is no absolute path defined.

5

In reply to DEGALA BALAJI:

You can try below,

  1. Register a variable in resource DB.
  2. set the variable according to the requirement in test or driver.
  3. get the variable at the Top level.
  4. Drive the DUT signal at Top level.
6

In reply to Preetampds:

I tried using this. But not working (Getting from Test or driver to Top is not Working). Even with Resource DB.

7

In reply to DEGALA BALAJI:

You have to instantiate your SV interface in the toplevel module of your verification environment.
Then pass this interface to the configuration database using the uvm_config_db set command.
In your testcase perform the uvm_config_db get command to retrieve the interface from the config db. Then you can do anything with this interface (driving/observing).
But you should ask if your testbench architecture is as required by the UVM. The standard architecture is that you do not deal with pin signals in the testcase.

8

In reply to chr_sue:

In above Preetampds Suggested to use resource DB for signals which i want to force for DUT Port Signals(not for interface.Either Preetampds or myself not disucssing about setting or getting interface from config DB). I tried using resource DB for driving the Signals in Test Case after that i set those to TOP_module(In the Top module DUT ports (which i want force) are assigned to signals which are getting from Resource DB from Test.

Best Regards
Balaji

9

In reply to DEGALA BALAJI:

The resource db is used by the config db. It is the layer below the config db and it is recommended to use the config db and not the resource db, because it offers you more flexibity.
You do not have any restrictions regarding observing or driving signals when you are using the config db.

10

In reply to DEGALA BALAJI:
See my DVCon paper The Missing Link: The Testbench to DUT Connection