Access directly the interface/variable of top in test, how can this happens?

Hi, all

I’m puzzled by one usage of accessing variable of top.


module top;

spi_if m_if;

initial begin
  run_test('test_a');
end

endmodule

class test_a extends uvm_test;
  ...
  
  function void build_phase(uvm_phase phase);
     force m_if.<sig_a> == 1;
  endfunction

endclass

why can this assignment – “force m_if.<sig_a> == 1;”, works without any error? there no virtual interface definition of m_if in class test_a. It seems m_if is the one in top, but can we use this without adding “top.m_if” (this the way I usually use), can “top.” be omitted? if yes? what let it works?

BR
Hubert

In reply to EnRoute_zt:

This reference should not work and should generate an error as it is ambiguous.

In general, hierarchical references are relative, and if they can not be resolved relatively, the tool will look at $root. The proper reference would be ‘top.m_if’ as you noted.

However, some tools will let you be lazy and do a recursive search from the top level to match an instance name. This can be very dangerous since the behavior isn’t clearly defined and you can have undesired results.

One additional note is that you should NEVER have hierarchical references outside of a SV class. If you use packages (as you should), you will receive an error.