12 sub phases

UVM
1

Hi all,
I read uvm_phasing in the cookbook given in the site. Phasing | Verification Academy

In phases, they are explaining about the 12 subtasks which runs in parallel with run_phase. In 12 sub phases, it is dealing with DUT in some way like reset,configure and all.It is mentioned that drivers, monitors should not implement this phases,only test/environment can do this.Then,Why is that so?

Thanks in advance,
Roopa

2

In reply to roopatoms:

How are you supposed to map those phases to the chip? Blocks and interfaces can be reset and configured independently. You might repeatedly reset and reconfigure one block, and never do that to another.

Example. A chip boots to an initial low power state. A small CPU is active and the fabric is on, but most blocks are asleep and in reset. What phase should all of your agents be in?

Now the test enables power for a block ( register accesses to power manager ), then enables clocks and releases reset for said block ( register accesses to clock and reset block ). What phases should all of your agents be in?

Now bring up another block, then put the first block back to sleep again.

The 12 sub-phases describe a linear progression, where all components operate in lock step. Reality is just not that simple.