Topics tagged UVM

Topic	Replies	Views	Activity
Confusion with the master monitor and slave monitor functionality UVM UVM , SPI-Test-Plan	3	140	December 22, 2025
UVM 1.2 new warning - a resource with meta characters in the field name has been created UVM UVM , uvm_reg_block , Resource_db , UVMRSRCNOREGEX , UVM-12 , uvm-warning	12	7415	December 18, 2025
Significance of 'contxt' Argument for create() functions of uvm_component_registry N uvm_object_registry UVM UVM , Significance-of-contxt-Argument-for-create-functions-of-uvm_component_registry-N-uvm_object_registry	2	1182	December 6, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	144	November 17, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	98	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	62	November 12, 2025
Vertical re-use (from block to sub-system/chip level) UVM UVM , reuse	5	3413	November 2, 2025
Why uvm_object_registry is called as lightweight proxy? UVM UVM	1	85	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	177	October 27, 2025
Multiple analysis ports to single implementation UVM SystemVerilog , UVM , analysis-port	8	312	October 23, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	178	October 21, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	135	October 21, 2025
Config db fatal isssue UVM OVM , SystemVerilog , UVM	1	117	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	111	October 15, 2025
Protected registers behavior implementation with RAL UVM UVM	1	81	October 8, 2025
Loop to randomize RAL fields across multiple registers SystemVerilog UVM	0	52	October 8, 2025
How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times UVM UVM	6	103	October 2, 2025
Facing error when passing arguments in the hierarchy when using $assertoff UVM UVM , assetions , assertoff	2	370	September 27, 2025
Project for self practice for creating TB UVM UVM	1	102	September 25, 2025
UVM INFO Message from SPELLCHK UVM UVM , UVM-UVM_INFO-uvm_spell_chkr	4	935	September 12, 2025
How to write scoreboard for in order and out of order transactions in AXI4 UVM UVM	1	290	September 12, 2025
Ral explicit prediction UVM UVM , RAL	1	100	September 9, 2025
[UVM BackDoor access] Is it possible to have multiple paths to register/memory/register block? UVM UVM , Backdoor-method	5	1457	September 4, 2025
c-uvm synchronization without DPI UVM UVM , Synchronization , C , co-sim	15	338	August 26, 2025
Agent to agent communication UVM UVM	2	113	August 18, 2025
Fatal Error in Visualizer during post_simulation UVM SystemVerilog , UVM , Visualizer-Debug-Environment	2	59	July 18, 2025
What is meant by read-modify -write in register access generally? UVM UVM	5	3372	July 16, 2025
Coverage bins sampling an uninitialized virtual interface object SystemVerilog UVM , Coverage	7	154	July 15, 2025
UVM Default and UVM ALL ON UVM UVM	2	250	July 7, 2025
Why do compare need to arguments, specially why second arguments of uvm_comparer comparer UVM UVM	4	106	July 2, 2025