|
Sequence which admits : No match v/s Hard Zero
|
|
8
|
440
|
December 27, 2023
|
|
Semaphore put method question
|
|
5
|
452
|
December 28, 2025
|
|
SVA to check a N-stage synchronizer output
|
|
9
|
119
|
December 18, 2025
|
|
Connection using modports with different signals
|
|
6
|
73
|
December 12, 2025
|
|
Deep copy using shallow copy
|
|
1
|
93
|
December 6, 2025
|
|
Once a certain sequence occurs that another seq shouldn't occur till simulation ends
|
|
8
|
685
|
December 4, 2025
|
|
Adding and deleting elements of dynamic type at same time
|
|
2
|
103
|
November 29, 2025
|
|
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules?
|
|
0
|
130
|
November 17, 2025
|
|
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses
|
|
2
|
93
|
November 13, 2025
|
|
Individual field access causes extra reads/writes?
|
|
5
|
57
|
November 12, 2025
|
|
Resume simulation when any 2 threads out of 3 get completed within fork-join_any
|
|
9
|
4308
|
November 12, 2025
|
|
Question regarding followed by operator in SVA (#-# and #=#
|
|
0
|
72
|
November 11, 2025
|
|
System verilog constraint help
|
|
2
|
146
|
November 11, 2025
|
|
Chained Implications in SVA
|
|
0
|
81
|
November 3, 2025
|
|
Why only ##1 (single delay operator) used in the case of multiple clock sequences?
|
|
2
|
689
|
November 3, 2025
|
|
restricting sequence as long as one variable is asserted
|
|
4
|
96
|
November 2, 2025
|
|
Paper: Understanding SVA Degeneracy
|
|
9
|
639
|
October 29, 2025
|
|
Multiple analysis ports to single implementation
|
|
8
|
291
|
October 23, 2025
|
|
How to properly extend a test case from different parents
|
|
2
|
176
|
October 21, 2025
|
|
How to deep copy UVM transaction containing queue of objects?
|
|
3
|
126
|
October 21, 2025
|
|
Is there an alternative to sum() Constraint
|
|
5
|
1914
|
October 19, 2025
|
|
What operators constitute a multi-threaded sequence
|
|
1
|
88
|
October 16, 2025
|
|
Config db fatal isssue
|
|
1
|
115
|
October 16, 2025
|
|
Getting last transaction in consumer repetitively even though producer is sending all transaction
|
|
3
|
108
|
October 15, 2025
|
|
SystemVerilog reason of not putting always in program block
|
|
1
|
95
|
October 15, 2025
|
|
Excluding the already defined bins
|
|
5
|
123
|
October 12, 2025
|
|
Need clarification on static method and non static method
|
|
11
|
4359
|
October 12, 2025
|
|
Random stability with non-random object
|
|
2
|
51
|
October 8, 2025
|
|
Assertion for clock gating
|
|
1
|
115
|
October 3, 2025
|
|
Dynamic Array- System Verilog
|
|
1
|
137
|
September 30, 2025
|