Topics tagged systemverilog-Arrays

Topic	Replies	Views	Activity
Randomizing packed array SystemVerilog SystemVerilog , array-slicing , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , SV-systemVerilog-constraints-array , systemverilog-arrays-struct-constraint-randomization-indexes	5	1812	May 8, 2021
Systemverilog enum help SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-enum-classes-constraints	3	1104	April 3, 2021
Why does an uninitialized fixed array get initialized to 0 or 1 using for loop SystemVerilog SystemVerilog , systemverilog-Arrays	2	809	February 6, 2021
With in system verilog not giving expected output SystemVerilog SystemVerilog , systemverilog-Arrays	2	825	February 6, 2021
Constarint for strobe signal in AXI SystemVerilog SystemVerilog , systemverilog-Arrays , constarint	2	2486	January 7, 2021
Generate non repeating values in an array of class SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-constraint	2	1867	January 6, 2021
Bit width from Array size SystemVerilog SystemVerilog , systemverilog-Arrays	4	2192	October 30, 2020
How can I succesfully cast a string queue element to an enumerated data type? SystemVerilog SystemVerilog , casting , systemverilog-Arrays , beginner , casting-of-enum	1	1192	October 29, 2020
Error while assigning an array in generate block SystemVerilog SystemVerilog , generate-block , Assertions-using-Generate-Block , assert-property , systemverilog-Arrays , Assignment-inside-generate-block	3	2907	September 11, 2020
How to implement static cast on array of enum while using bitstream operator SystemVerilog SystemVerilog , Streaming-Operator , systemverilog-Arrays , casting-of-enum	5	4038	June 14, 2020
[SV LRM 2017] What is intend of using sort in structure? SystemVerilog SystemVerilog , systemverilog-Arrays	2	786	June 8, 2020
[SV LRM 2017] Finding unique strings which are in lowercase SystemVerilog SystemVerilog , systemverilog-Arrays	3	781	May 31, 2020
Sum the array values SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes	9	1815	May 19, 2020
Indexing an array through an enum datatype SystemVerilog SystemVerilog , enum , systemverilog-Arrays , FPGA , systemverilog-enum-classes-constraints	1	4193	April 1, 2020
Find index in 2D array using find_index SystemVerilog SystemVerilog , systemverilog-Arrays , queues-systemverilog , find_index	1	3326	March 15, 2020
Passing a String Array from C (C++) into SV using DPI SystemVerilog SystemVerilog , DPI , systemverilog-Arrays	3	6386	March 13, 2020
How to implement an assosiative array functionality using dynamic array SystemVerilog SystemVerilog , dynamic-arrays , associative-array , systemverilog-Arrays	6	1762	December 25, 2019
An empty loop variable with multi dimension of the array not working SystemVerilog SystemVerilog , systemverilog-Arrays , constraint-array	2	1343	October 30, 2019
Queue SystemVerilog SystemVerilog , systemverilog-Arrays	1	923	July 29, 2019
Transfer Data from in reg to other reg SystemVerilog SystemVerilog , systemverilog-Arrays	1	922	April 17, 2019
Work around for variable width bit slicing? SystemVerilog SystemVerilog , systemverilog-Arrays , uvm-verilog	1	1292	March 14, 2019
Error when using a constant as bit-select SystemVerilog SystemVerilog , systemverilog-Arrays	8	1879	March 7, 2019
Unconstrained Arrays equivalent in SystemVerilog SystemVerilog SystemVerilog , VHDL , systemverilog-Arrays	2	2573	March 1, 2019
Simple testbench for required specifications SystemVerilog SystemVerilog , system-verilog-testbench , block-level-testcase , systemverilog-Arrays , clocking-block-testbench	1	1006	January 4, 2019
Extracting data slice from an array SystemVerilog SystemVerilog , systemverilog-Arrays	4	1142	December 23, 2018
Pass array to a function SystemVerilog SystemVerilog , systemverilog-Arrays	5	22847	December 15, 2018
Zero bit width array? SystemVerilog SystemVerilog , systemverilog-Arrays	8	8918	December 6, 2018
Constraint a random array UVM UVM , associative-array-inline-constraint , systemverilog-Arrays	5	1074	October 2, 2018
Array Constraint SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays	3	1605	September 16, 2018
Two dimensional array SystemVerilog SystemVerilog , systemverilog-Arrays , two-dimensional-array	1	1350	September 14, 2018

Randomizing packed array

SystemVerilog , array-slicing , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , SV-systemVerilog-constraints-array , systemverilog-arrays-struct-constraint-randomization-indexes