Topics tagged interface

Topic	Replies	Views	Activity
How do we connect two different VIPs back to back? UVM UVM , interface , VIP , architecture , USB-30 , back-to-back	1	1389	September 24, 2018
Virtual interface and multiple drivers (signal drivers not UVM drivers) UVM UVM , virtual-interface , interface	8	3808	August 10, 2018
Interface with a port SystemVerilog SystemVerilog , interface	2	1518	August 9, 2018
Clocking Block Skew @ Simulation Wave SystemVerilog SystemVerilog , UVM , interface , Clocking-Block , Skew , Delay	2	2852	July 7, 2018
SV interface - parameter vs local signal UVM UVM , interface	3	1678	February 1, 2018
Tristate handling in interface SystemVerilog SystemVerilog , interface , tristate	2	3033	June 12, 2017
What is interface::self SystemVerilog SystemVerilog , UVM , interface	2	3226	August 17, 2016
Why use "wire logic" as the data type for the interface signals? SystemVerilog SystemVerilog , interface , wire-logic	1	6108	February 2, 2016
Converting a module to/using a module in OVM? OVM OVM , configuration , interface , module	4	2481	November 20, 2015
Same interface, different monitors UVM UVM , interface , multiple-interface , monitor , multiple-agents	1	1625	October 28, 2015
Connecting/binding interface to interface SystemVerilog SystemVerilog , interface-connections , bind , interface , sytem-verilog	6	4818	September 11, 2015
Connecting two modules using an interface SystemVerilog SystemVerilog , interface	2	6169	September 9, 2015
Passing config parameters to interface UVM UVM , interface , Parameters	2	3329	August 10, 2015
How to pass clock signal to a class inside a program? SystemVerilog SystemVerilog , class , interface , program	4	4487	June 25, 2015
Can modports be used to isolate logic signals in an interface from tasks? SystemVerilog SystemVerilog , modport , interface , VHDL , tasks	2	2634	June 11, 2015
Using modports to restrict access to interface signals SystemVerilog SystemVerilog , modport , interface	1	3361	May 14, 2015
Is it valid to pass argument via ref in Interface? SystemVerilog SystemVerilog , System-Verilog , interface , argument-pass-by-ref	2	1712	January 5, 2015
Driver ,Interface connection to RTL Strange Error SystemVerilog SystemVerilog , System-Verilog , interface , driver	2	1859	October 1, 2014
SV-interface SystemVerilog SystemVerilog , interface	1	1596	August 18, 2014
Interfaces SystemVerilog SystemVerilog , interface	1	1522	August 5, 2014
Sequence coverage in Interface clocking block Coverage Coverage , interface , clocking-block-sequence-coverage	1	1763	June 13, 2014
FATAL ERROR while loading design SystemVerilog SystemVerilog , System-Verilog , virtual-interface , FATAL-ERROR , SDRAM , interface	3	4514	March 12, 2014