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How do we connect two different VIPs back to back?
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1
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1389
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September 24, 2018
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Virtual interface and multiple drivers (signal drivers not UVM drivers)
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8
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3808
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August 10, 2018
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Interface with a port
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2
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1518
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August 9, 2018
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Clocking Block Skew @ Simulation Wave
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2
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2852
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July 7, 2018
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SV interface - parameter vs local signal
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3
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1678
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February 1, 2018
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Tristate handling in interface
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2
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3033
|
June 12, 2017
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What is interface::self
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2
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3226
|
August 17, 2016
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Why use "wire logic" as the data type for the interface signals?
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1
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6108
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February 2, 2016
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Converting a module to/using a module in OVM?
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4
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2481
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November 20, 2015
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Same interface, different monitors
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1
|
1625
|
October 28, 2015
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Connecting/binding interface to interface
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6
|
4818
|
September 11, 2015
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|
Connecting two modules using an interface
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2
|
6169
|
September 9, 2015
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Passing config parameters to interface
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2
|
3329
|
August 10, 2015
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How to pass clock signal to a class inside a program?
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4
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4487
|
June 25, 2015
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Can modports be used to isolate logic signals in an interface from tasks?
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2
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2634
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June 11, 2015
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Using modports to restrict access to interface signals
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1
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3361
|
May 14, 2015
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Is it valid to pass argument via ref in Interface?
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2
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1712
|
January 5, 2015
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Driver ,Interface connection to RTL Strange Error
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2
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1859
|
October 1, 2014
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SV-interface
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|
1
|
1596
|
August 18, 2014
|
|
Interfaces
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|
1
|
1522
|
August 5, 2014
|
|
Sequence coverage in Interface clocking block
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|
1
|
1763
|
June 13, 2014
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FATAL ERROR while loading design
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3
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4514
|
March 12, 2014
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