Topics tagged constraints

Topic	Replies	Views	Activity
Constraint for memories SystemVerilog SystemVerilog , constraints	6	5993	March 4, 2025
Valid Data Filter SystemVerilog SystemVerilog , System-Verilog , constraint , constraint-randomization , Verilog , constraints , systemverilog-constraint	2	64	February 16, 2025
Integer dynamic array sum constraint not working SystemVerilog constraints	4	40	February 9, 2025
Bit Constraints of each element in array SystemVerilog constraints	6	176	November 25, 2024
Values injection into randomize variable SystemVerilog SystemVerilog , constraints	8	169	September 2, 2024
Prime numbers constraint SystemVerilog SystemVerilog , system-verilog-constraints , constraints , uvm-sv-constraints	1	290	July 17, 2024
Constraining address generation for each block of memory in cyclic order SystemVerilog SystemVerilog , constraint-randomization , constraints	2	302	March 18, 2024
Function call inside constraint SystemVerilog constraints	1	299	March 8, 2024
Creating random constraints for overlapping sequence detector SystemVerilog SystemVerilog , constraint-randomization , constraints	1	429	January 29, 2024
How is this both constraint working same? SystemVerilog constraint-randomization , constraints , slove-before-constraint	4	309	January 13, 2024
Conditional inline constraint SystemVerilog System-Verilog , constraints	4	642	December 20, 2023
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	22	11458	April 15, 2023
Constraint involving queues and arrays SystemVerilog SystemVerilog , constraints	9	7094	February 13, 2023
Percentage weighted distribution of SV Constraints SystemVerilog SystemVerilog , constraints , constraint-dist , weighted-distribution	4	1945	March 10, 2022
Number of solutions of a randomization SystemVerilog SystemVerilog , randomization , constraints	8	1726	December 28, 2021
Constraint for address to be inside 4k boundary SystemVerilog SystemVerilog , constraints	12	8323	September 3, 2021
Unable to use randc for uniqueness SystemVerilog SystemVerilog , Specific-randomization-in-system-verilog-class , constraints	2	829	August 18, 2021
I have been trying to solve this constraints problem given below SystemVerilog SystemVerilog , constraints , SV-systemVerilog-constraints-array	2	1488	May 2, 2021
How do I constrain data within hierarchy at test level? UVM UVM , constraints	8	2857	April 14, 2021
Constraint to make sure a matrix inverse exists SystemVerilog SystemVerilog , constraints , matrix	7	2610	November 25, 2020
Repetition multiplier when variable SystemVerilog SystemVerilog , constraints	4	1507	November 11, 2020
Constraint the 2-D array size SystemVerilog SystemVerilog , randomization , constraints , 2-dimensional-dynamic-array-randomization	2	2019	June 21, 2020
Can we use Ternary operator in Constraints? SystemVerilog SystemVerilog , constraints	7	3107	May 21, 2020
While randomizing 3 values, if one value repeat for 2 times, then other two values should repeat for one time SystemVerilog SystemVerilog , randomization , constraints	3	1352	January 30, 2020
Difference in overflow while using byte and int SystemVerilog SystemVerilog , systemverilog-datatypes , constraints	5	1432	January 25, 2020
Constraint to cause a value to be within a set defined in a dynamic array SystemVerilog SystemVerilog , UVM , Dynamic-Array , constraints	1	1061	December 18, 2019
Constraint Randomization SystemVerilog SystemVerilog , constraints	1	1061	December 2, 2019
SV Constraint using array of weights UVM SystemVerilog , UVM , randomization , constraints	2	1872	November 27, 2019
Parameterizing a Class With run-time variable? SystemVerilog SystemVerilog , randomization , constraints	5	1864	August 26, 2019
How to detect number of one's in an array and each time one bit should be asserted and the remaining bits should be 0's by using SV constraints? SystemVerilog SystemVerilog , constraints	1	5324	July 2, 2019

Constraint for memories

SystemVerilog

SystemVerilog , constraints

6

5993

March 4, 2025

Valid Data Filter

SystemVerilog

SystemVerilog , System-Verilog , constraint , constraint-randomization , Verilog , constraints , systemverilog-constraint

2

64

February 16, 2025

Integer dynamic array sum constraint not working

SystemVerilog

constraints

4

40

February 9, 2025

Bit Constraints of each element in array

SystemVerilog

constraints

6

176

November 25, 2024

Values injection into randomize variable

SystemVerilog

SystemVerilog , constraints

8

169

September 2, 2024

Prime numbers constraint

SystemVerilog

SystemVerilog , system-verilog-constraints , constraints , uvm-sv-constraints

1

290

July 17, 2024

Constraining address generation for each block of memory in cyclic order

SystemVerilog

SystemVerilog , constraint-randomization , constraints

2

302

March 18, 2024

Function call inside constraint

SystemVerilog

constraints

1

299

March 8, 2024

Creating random constraints for overlapping sequence detector

SystemVerilog

SystemVerilog , constraint-randomization , constraints

1

429

January 29, 2024

How is this both constraint working same?

SystemVerilog

constraint-randomization , constraints , slove-before-constraint

4

309

January 13, 2024

Conditional inline constraint

SystemVerilog

System-Verilog , constraints

4

642

December 20, 2023

Interview question on constraint

SystemVerilog

SystemVerilog , constraints , uvm-sv-constraints

22

11458

April 15, 2023

Constraint involving queues and arrays

SystemVerilog

SystemVerilog , constraints

9

7094

February 13, 2023

Percentage weighted distribution of SV Constraints

SystemVerilog

SystemVerilog , constraints , constraint-dist , weighted-distribution

4

1945

March 10, 2022

Number of solutions of a randomization

SystemVerilog

SystemVerilog , randomization , constraints

8

1726

December 28, 2021

Constraint for address to be inside 4k boundary

SystemVerilog

SystemVerilog , constraints

12

8323

September 3, 2021

Unable to use randc for uniqueness

SystemVerilog

SystemVerilog , Specific-randomization-in-system-verilog-class , constraints

2

829

August 18, 2021

I have been trying to solve this constraints problem given below

SystemVerilog

SystemVerilog , constraints , SV-systemVerilog-constraints-array

2

1488

May 2, 2021

How do I constrain data within hierarchy at test level?

UVM

UVM , constraints

8

2857

April 14, 2021

Constraint to make sure a matrix inverse exists

SystemVerilog

SystemVerilog , constraints , matrix

7

2610

November 25, 2020

Repetition multiplier when variable

SystemVerilog

SystemVerilog , constraints

4

1507

November 11, 2020

Constraint the 2-D array size

SystemVerilog

SystemVerilog , randomization , constraints , 2-dimensional-dynamic-array-randomization

2

2019

June 21, 2020

Can we use Ternary operator in Constraints?

SystemVerilog

SystemVerilog , constraints

7

3107

May 21, 2020

While randomizing 3 values, if one value repeat for 2 times, then other two values should repeat for one time

SystemVerilog

SystemVerilog , randomization , constraints

3

1352

January 30, 2020

Difference in overflow while using byte and int

SystemVerilog

SystemVerilog , systemverilog-datatypes , constraints

5

1432

January 25, 2020

Constraint to cause a value to be within a set defined in a dynamic array

SystemVerilog

SystemVerilog , UVM , Dynamic-Array , constraints

1

1061

December 18, 2019

Constraint Randomization

SystemVerilog

SystemVerilog , constraints

1

1061

December 2, 2019

SV Constraint using array of weights

UVM

SystemVerilog , UVM , randomization , constraints

2

1872

November 27, 2019

Parameterizing a Class With run-time variable?

SystemVerilog

SystemVerilog , randomization , constraints

5

1864

August 26, 2019

How to detect number of one's in an array and each time one bit should be asserted and the remaining bits should be 0's by using SV constraints?

SystemVerilog

SystemVerilog , constraints

1

5324

July 2, 2019