# Wire vs Logic

**URL:** <https://verificationacademy.com/forums/t/wire-vs-logic/34070>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, logic, wire, Mapping-data-types, ports\
**Created:** [February 10, 2018, 10:02pm UTC](https://verificationacademy.com/forums/t/wire-vs-logic/34070 "2018-02-10T22:02:43Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![manjush](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/d9b06d/32.png) [@manjush](https://verificationacademy.com/forums/u/manjush)\
**Post date:** [February 10, 2018, 10:02pm UTC](https://verificationacademy.com/forums/t/wire-vs-logic/34070/1 "2018-02-10T22:02:43Z")

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Hello guys

Can anyone explain whats the basic difference between wire and logic?  
How type and data type is differentiated?  
I know var / wire is a type and logic / bit / byte / … are all data types, but whats the difference between both??

And please let me know why am getting error on the below code!!!

```verilog
module strobe_test(input logic a, b, clk, output logic y);
always_ff @(posedge clk) begin
	y <= a + b;
end

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
	a = 0; b = 0;
	#10 a = 0; b = 1;
	#10 a = 1; b = 0;
	#10 a = 1; b = 1;
	#20 $stop;
end

endmodule : strobe_test

```

Errors →

# – Compiling module strobe\_test

# \*\* Error: strobe\_test.sv(7): (vlog-2110) Illegal reference to net “clk”.

# \*\* Error: strobe\_test.sv(8): (vlog-2110) Illegal reference to net “clk”.

# \*\* Error: strobe\_test.sv(12): (vlog-2110) Illegal reference to net “a”.

# \*\* Error: strobe\_test.sv(12): (vlog-2110) Illegal reference to net “b”.

# \*\* Error: strobe\_test.sv(13): (vlog-2110) Illegal reference to net “a”.

# \*\* Error: strobe\_test.sv(13): (vlog-2110) Illegal reference to net “b”.

# \*\* Error: strobe\_test.sv(14): (vlog-2110) Illegal reference to net “a”.

# \*\* Error: strobe\_test.sv(14): (vlog-2110) Illegal reference to net “b”.

# \*\* Error: strobe\_test.sv(15): (vlog-2110) Illegal reference to net “a”.

# \*\* Error: strobe\_test.sv(15): (vlog-2110) Illegal reference to net “b”.

And someone please explain what would be the default type and data type of ports, how port definitions vary on the usage of the same??

Thanks  
Manjush

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [February 10, 2018, 10:23pm UTC](https://verificationacademy.com/forums/t/wire-vs-logic/34070/2 "2018-02-10T22:23:11Z")

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_In reply to [manjush\_pv](https://verificationacademy.com/forums/t/wire-vs-logic/34070):_

See [What's the deal with those wire’s and reg’s in Verilog - Verification Horizons](https://blogs.sw.siemens.com/verificationhorizons/2013/05/03/wire-vs-reg/) and [Usage of Var - SystemVerilog - Verification Academy](https://verificationacademy.com/forums/systemverilog/usage-var#reply-42240)

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**Author:** ![manjush](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/d9b06d/32.png) [@manjush](https://verificationacademy.com/forums/u/manjush)\
**Post date:** [February 11, 2018, 1:56am UTC](https://verificationacademy.com/forums/t/wire-vs-logic/34070/3 "2018-02-11T01:56:34Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/wire-vs-logic/34070/2):_

Thanks Dave, that helped a much.