In reply to cuonghl:
A properly thought out compilation methodology using packages should not need compile guards in SystemVerilog. If you order your `include files in a package correctly, all of your classes and macros defines get compiled once.
In reply to cuonghl:
A properly thought out compilation methodology using packages should not need compile guards in SystemVerilog. If you order your `include files in a package correctly, all of your classes and macros defines get compiled once.