We use the below example in some of our advanced SV training sessions/bootcamps. Crux of it is to use SVA’s “bind” feature and have the interface use all signals required as port level signals. Its a demo code showing how to write SVA on those internal signals. Doing a virtual interface say through a uvm_config_db::set() is a natural extension. Do let me know if you need assistance in that.
HTH
Ajeetha, CVC
import uvm_pkg::*;
`include "uvm_macros.svh"
interface mon_if (input logic clk, int_sig1, int_sig2);
a_sig1_then_sig2 : assert property ( @(posedge clk)
int_sig1 |=> int_sig2) else
`uvm_error ("SVA", "int_sig2 didn't follow int_sig1");
endinterface : mon_if
module m;
logic clk, int_sig1, int_sig2;
initial begin : clk_gen
clk <= 1'b0;
forever #10 clk <= !clk;
end : clk_gen
default clocking @ (posedge clk);
endclocking
initial begin : test
int_sig1 <= 1'b0;
int_sig2 <= 1'b0;
##10;
int_sig1 <= 1'b1;
##1;
int_sig1 <= 1'b0;
##10;
$finish;
end : test
endmodule : m
bind m mon_if mon_if_0 (.*);
Here is a sample output from a Questa run:
** Error: int_sig2 didn’t follow int_sig1