# Wait and @event syntax difference issues

**URL:** <https://verificationacademy.com/forums/t/wait-and-event-syntax-difference-issues/39032>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [April 28, 2021, 9:37pm UTC](https://verificationacademy.com/forums/t/wait-and-event-syntax-difference-issues/39032 "2021-04-28T21:37:30Z")\
**Posts on this page:** 1\
**Showing post:** 6

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [April 30, 2021, 8:02pm UTC](https://verificationacademy.com/forums/t/wait-and-event-syntax-difference-issues/39032/6 "2021-04-30T20:02:27Z")

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_In reply to [megamind](https://verificationacademy.com/forums/t/wait-and-event-syntax-difference-issues/39032/5):_

You need to go back and edit your post as your image is not visible. A [link to EDAPlayground](https://blogs.sw.siemens.com/verificationhorizons/2020/04/29/forums-with-edaplayground/) would be much better.

The 2 big differences between event controls @(posedge signal) and wait(signal)

1. The transition from 0 to 1 must not have already happened for @(posedge signal) when encountering that event control. It really should read as “wait for the _next_ transition to 1”
2. wait(signal) will not block if signal is already 1. If you have this construct in a loop without any other blocking event controls, you get an infinite 0-delay loop.

So they only behave the same if signal is not 0 at the point when encountering either event control.

When you say that a signal is synchronous, that means you only want to sample its value on a clock edge. You would want to use @(posedge clk iff (signal))

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