Virtual interface resolution cannot find a matching instance for 'virtual apb_if'

do run.do
Hi can anyone tell me how to resolve this error ?

# ** Warning: (vlib-34) Library already exists at "work".
# 
# Modifying modelsim.ini
# QuestaSim-64 vlog 10.2c Compiler 2013.07 Jul 19 2013
# -- Compiling package uvm_pkg (uvm-1.1d Built-in)
# -- Compiling interface apb_if
# -- Compiling package top_sv_unit
# -- Importing package uvm_pkg (uvm-1.1d Built-in)
# -- Compiling module apb
# -- Compiling interface apb_if
# -- Compiling module top
# 
# Top level modules:
# 	top
# vsim +UVM_TESTNAME=test +define+UVM_CMDLINE_NO_DPI -l simulation.log -c -sv_seed random top 
# Loading sv_std.std
# Loading work.uvm_pkg(fast)
# Loading work.top_sv_unit(fast)
# ** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled "questa_uvm_pkg" can be found.
# 
# This also means that later if you turn on UVM-aware debugging your debug simulations may have
# 
# different random seeds from your non-debug simulations.
# 
# Loading work.top(fast)
# Loading work.apb(fast)
# ** Fatal: (vsim-8451) ../top/top.sv(12): Virtual interface resolution cannot find a matching instance for 'virtual apb_if'.
#    Time: 0 ns  Iteration: 0  Instance: /top File: ../top/top.sv
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design 
#        Pausing macro execution 
# MACRO ./run.do PAUSED at line 16

Hard to help you without seeing any code. Perhaps you declared a virtual interface that was parameterized, and there was no matching instance. Also, you are running an extremely old version of a tool.

This is the code
i have tried by removing virtual keyword but still its showing error

`include"uvm_pkg.sv"
import uvm_pkg::*;

include "../RTL/apb.v" include “…/RTL/apb_if.sv”

module top();
bit clk;
virtual apb_if vif;
always #10 clk=~clk;

apb DUT (.pclk(vif.pclk),.presetn(vif.presetn),.psel(vif.psel),.penable(vif.penable),.pwrite(vif.pwrite),.paddr(vif.paddr),.pwdata(vif.pwdata),.prdata(vif.prdata),.pready(vif.pready),.pslverr(vif.pslverr));
initial
begin
uvm_config_db#(virtual apb_if)::set(null,“*”,“vif”,vif);
end
initial
begin
run_test(“test”);
end
endmodule

A virtual interface variable needs to hold a handle to an actual interface instance. Your DUT needs to be connected to an actual interface instance. An actual interface gets instantiated just like a module.

module top();
bit clk;
always #10 clk=~clk;
apb_if intf(clk); // I'm guessing your interface has a clk port
virtual apb_if vif = intf;

apb DUT (.pclk(intf.pclk),.presetn(intf.presetn),.psel(intf.psel),.penable(intf.penable),.pwrite(intf.pwrite),.paddr(intf.paddr),.pwdata(intf.pwdata),.prdata(intf.prdata),.pready(intf.pready),.pslverr(intf.pslverr));

as i have checked my interface doesn’t contain clk port
and can you please tell me is this a correct way to declare uvm_config_db set method?
uvm_config_db#(virtual apb_if)::set(null,“*”,“vif”,vif);

It looks OK.

I suggest you study a working example instead of trying to ask one question at a time.

okay,sure i will look into it
Thank you for assistance!