# Verifying synchronours fifo

**URL:** <https://verificationacademy.com/forums/t/verifying-synchronours-fifo/51462>\
**Category:** SystemVerilog\
**Created:** [November 11, 2025, 8:46pm UTC](https://verificationacademy.com/forums/t/verifying-synchronours-fifo/51462 "2025-11-11T20:46:02Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![Nitinreddy](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/n/e9a140/32.png) [@Nitinreddy](https://verificationacademy.com/forums/u/Nitinreddy)\
**Post date:** [November 11, 2025, 8:46pm UTC](https://verificationacademy.com/forums/t/verifying-synchronours-fifo/51462/1 "2025-11-11T20:46:02Z")

</div>

Here is my simple design of synchronous fifo:

```verilog
module sync_fifo #(parameter DEPTH = 8, WIDTH = 16) (
  input bit clk,
  rst_n,
  rd_en,
  wr_en,
  input logic [WIDTH-1 : 0] data_in,
  output logic [WIDTH-1 : 0] data_out,
  output bit full,
  empty
);

  logic [$clog2(DEPTH)-1 : 0] rd_ptr;
  logic [$clog2(DEPTH)-1 : 0] wr_ptr;

  logic [WIDTH-1 : 0] fifo[DEPTH-1 : 0];
  logic [$clog2(DEPTH)-1:0]count;

  always@(posedge clk) begin
    $display($time,"[DUT] wr-en = %0d",wr_en);
  end

  always_ff @(posedge clk) begin
    if(!rst_n) begin
      wr_ptr <=0;
    end
    else begin
      if(wr_en && !full) begin
        fifo[wr_ptr] <= data_in;
        wr_ptr <= wr_ptr +1;
      end
      else $display("[DUT] write failed");
    end
  end

  always_ff @(posedge clk) begin
    if(!rst_n) begin
      rd_ptr <= 0;
    end
    else begin
      if(rd_en && !empty) begin
        data_out <= fifo[rd_ptr];
        rd_ptr <= rd_ptr +1;
      end
    end
  end

  always_ff @(posedge clk) begin
    if(!rst_n) begin
      count <= 0;
    end
    else begin
      case({wr_en,rd_en})
        2'b10 : count <= count + 1;
        2'b01 : count <= count - 1;
        default : count <= count;
      endcase
    end
  end

  assign empty = (count == 0) ? 1'b1 : 1'b0;
  assign full = (DEPTH == count) ? 1'b1 : 1'b0;

endmodule

```

I wrote a simple testbench to verify it :

 ![Screenshot 2025-11-11 114929](https://verificationacademy.com/forums/uploads/default/original/2X/8/8250e97295296b8c3fe1cf06b87bdda7b561479a.png)

![]()But the write operation is not performing as desired . Could someone please explain what’s happening?

 ![Screenshot 2025-11-11 115138](https://verificationacademy.com/forums/uploads/default/original/2X/4/4cea47aee4c372df372d04f1687b855db3d4d45d.png)

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<div class="post-metadata">

**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [November 11, 2025, 9:15pm UTC](https://verificationacademy.com/forums/t/verifying-synchronours-fifo/51462/2 "2025-11-11T21:15:03Z")

</div>

Please post your testbench code as text and not an image. Or better yet, post the complete example to EDA Playground so that others can run your code and give you an answer.

---

<div class="post-metadata">

**Author:** ![Nitinreddy](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/n/e9a140/32.png) [@Nitinreddy](https://verificationacademy.com/forums/u/Nitinreddy)\
**Post date:** [November 11, 2025, 10:20pm UTC](https://verificationacademy.com/forums/t/verifying-synchronours-fifo/51462/4 "2025-11-11T22:20:13Z")

</div>

> **[EDA Playground](https://www.edaplayground.com/x/gAbX)**
>
> Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

---

<div class="post-metadata">

**Author:** ![gsulliva](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/g/eb9ed0/32.png) [@gsulliva](https://verificationacademy.com/forums/u/gsulliva)\
**Post date:** [November 11, 2025, 10:40pm UTC](https://verificationacademy.com/forums/t/verifying-synchronours-fifo/51462/5 "2025-11-11T22:40:11Z")

</div>

There are several problems.

You wanted to do 8 writes, but you only do 7 writes. You set wr\_en to 0 too early. Do it after this line, not before it:

repeat(1) @(posedge clk);

Similarly, you only do 7 reads because you set rd\_en too early.

You should debug with waveforms, not display statements. You would see that the fifo only got 7 words, not 8.

For all the synchronous inputs to the dut, you need to use nonblocking assignments, like wr\_en \<= 1. You have simulation race conditions using blocking assignments.