# UVM

**URL:** <https://verificationacademy.com/forums/t/uvm/34687>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [July 17, 2018, 5:47am UTC](https://verificationacademy.com/forums/t/uvm/34687 "2018-07-17T05:47:28Z")\
**Posts on this page:** 1\
**Showing post:** 9

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**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\
**Post date:** [July 18, 2018, 5:16am UTC](https://verificationacademy.com/forums/t/uvm/34687/9 "2018-07-18T05:16:16Z")

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_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/8):_

yes, Reset isn’t long enough. here i am attaching code after increasing reset duration to 20 and it is working as per your expectations.

Link:-

> **[EDA Playground](https://www.edaplayground.com/x/4QCB)**
>
> Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

Regards,  
Mitesh

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