# UVM

**URL:** <https://verificationacademy.com/forums/t/uvm/34687>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [July 17, 2018, 5:47am UTC](https://verificationacademy.com/forums/t/uvm/34687 "2018-07-17T05:47:28Z")\
**Posts on this page:** 1\
**Showing post:** 35

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**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 23, 2018, 7:30am UTC](https://verificationacademy.com/forums/t/uvm/34687/35 "2018-07-23T07:30:48Z")

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_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/34):_

in the body method of your sequence you can implement a loop like this

```verilog
repeat (100)
  `uvm_do_with(req, with {your constraints;})

```

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