# UVM

**URL:** <https://verificationacademy.com/forums/t/uvm/34687>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [July 17, 2018, 5:47am UTC](https://verificationacademy.com/forums/t/uvm/34687 "2018-07-17T05:47:28Z")\
**Posts on this page:** 20\
**Page:** 2

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**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 19, 2018, 9:45am UTC](https://verificationacademy.com/forums/t/uvm/34687/21 "2018-07-19T09:45:42Z")

</div>

I have now included agent configuration and environment configuration files. But it is showing errors, i dont know what those means. Could you please help me out with this?

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<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 19, 2018, 9:46am UTC](https://verificationacademy.com/forums/t/uvm/34687/22 "2018-07-19T09:46:51Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/21):_

> I have now included agent configuration and environment configuration files. But it is showing errors, i dont know what those means. Could you please help me out with this?

Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(14)  
\*\* at uvm\_sd\_agent.sv(35): Invalid type ‘fsm\_agent\_config’. Please check the type of the variable ‘ag\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(14)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_agent.sv(48)  
\*\* at uvm\_sd\_agent.sv(48): (vlog-2730) Undefined variable: ‘ag\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(14)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_agent.sv(48)  
\*\* at uvm\_sd\_agent.sv(48): (vlog-2730) Undefined variable: ‘ag\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(14)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_agent.sv(48)  
\*\* at uvm\_sd\_agent.sv(48): (vlog-2730) Undefined variable: ‘ag\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(14)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_agent.sv(48)  
\*\* at uvm\_sd\_agent.sv(48): (vlog-2730) Undefined variable: ‘ag\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(14)  
\*\* at uvm\_sd\_agent.sv(69): (vlog-2730) Undefined variable: ‘fsm\_agent\_config’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(17)  
\*\* at uvm\_sd\_environment.sv(35): Invalid type ‘fsm\_env\_config’. Please check the type of the variable ‘env\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(17)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_environment.sv(47)  
\*\* at uvm\_sd\_environment.sv(47): (vlog-2730) Undefined variable: ‘env\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(17)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_environment.sv(47)  
\*\* at uvm\_sd\_environment.sv(47): (vlog-2730) Undefined variable: ‘env\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(17)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_environment.sv(47)  
\*\* at uvm\_sd\_environment.sv(47): (vlog-2730) Undefined variable: ‘env\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(17)  
\*\* while parsing macro expansion: ‘uvm\_field\_object’ starting at uvm\_sd\_environment.sv(47)  
\*\* at uvm\_sd\_environment.sv(47): (vlog-2730) Undefined variable: ‘env\_cg’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(17)  
\*\* at uvm\_sd\_environment.sv(68): (vlog-2730) Undefined variable: ‘fsm\_env\_config’.  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(17)  
\*\* at uvm\_sd\_environment.sv(74): Failed to find name ‘type\_id’ in specified scope  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(20)  
\*\* at uvm\_sd\_tbtop.sv(19): near “module”: syntax error, unexpected module, expecting function or task  
End time: 14:30:34 on Jul 19,2018, Elapsed time: 0:00:01  
Errors: 14, Warnings: 0  
[muthamizhselvi.m@chennai UVM\_PROJECT]$

Actually what do these errors mean? Where should i correct them actually?

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<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 19, 2018, 10:48am UTC](https://verificationacademy.com/forums/t/uvm/34687/23 "2018-07-19T10:48:25Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/22):_

It looks loke your agent and env configurations are not visible in the compiled library.  
Did you really compile the configurations and are they compile in the right order?

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<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 19, 2018, 10:56am UTC](https://verificationacademy.com/forums/t/uvm/34687/24 "2018-07-19T10:56:17Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/23):_

yes, i have changed the order. Now I am getting these 2 errors.

\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(18)  
\*\* at uvm\_sd\_environment.sv(76): Failed to find name ‘type\_id’ in specified scope  
\*\* Error: \*\* while parsing file included at uvm\_sd\_allfiles.sv(20)  
\*\* at uvm\_sd\_tbtop.sv(19): near “module”: syntax error, unexpected module, expecting function or task  
End time: 15:43:48 on Jul 19,2018, Elapsed time: 0:00:00  
Errors: 2, Warnings: 0

---

<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 19, 2018, 11:39am UTC](https://verificationacademy.com/forums/t/uvm/34687/25 "2018-07-19T11:39:59Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/24):_

Because I do not know what uvm\_sd\_allfiles.sv and uvm\_sd\_tbtop.sv is I can’t answer your question.  
‘Failed to find name ‘type\_id’ in specified scope’ points to a problem with the macros.

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<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 19, 2018, 12:23pm UTC](https://verificationacademy.com/forums/t/uvm/34687/26 "2018-07-19T12:23:13Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/25):_

//============================================================================  
// CONFIDENTIAL and Copyright (C) 2010 Test and Verification Solutions Ltd  
//============================================================================  
// Contents : File for uvm\_sd\_tbtop.svh  
//  
// Brief description : Top file which runs the whole Environment  
//  
// Known exceptions to rules :  
//  
//============================================================================  
// Author :  
// Created on :  
// File Id : uvm\_sd\_tbtop.sv  
//============================================================================

`ifndef UVM_SD_TBTOP_SV `define UVM\_SD\_TBTOP\_SV

module tb\_top();

bit clk=1;  
bit rst;

//clock generation

always #2 clk = ~clk;

//reset generation

initial  
begin  
rst=1;  
#5 rst=0;  
end

//Interface instance

intf vif(clk,rst);

//DUT instance

fsm1 DUT(.clk(vif.clk),  
.rst(vif.rst),  
.in(vif.in),  
.out(vif.out),  
.state(vif.state));

//Setting configuration database

initial  
begin  
uvm\_config\_db#(virtual intf)::set(uvm\_root::get(),“\*”,“vif”,vif);  
$dumpfile(“dump.vcd”);  
$dumpvars;  
end

initial  
begin  
run\_test(“test”);  
end

endmodule : tb\_top

`endif

//COMPILE LIST

`include “uvm\_macros.svh”  
import uvm\_pkg::\*;

`include "fsm1.sv" `include “uvm\_sd\_interface.sv”  
`include "uvm_sd_seq_item.sv" `include “uvm\_sd\_sequence.sv”  
`include "uvm_sd_sequencer.sv" `include “uvm\_sd\_driver.sv”  
`include "uvm_sd_monitor.sv" `include “uvm\_sd\_agent\_config.sv”  
`include "uvm_sd_agent.sv" `include “uvm\_sd\_scoreboard.sv”  
`include "uvm_sd_env_config.sv" `include “uvm\_sd\_environment.sv”  
`include "uvm_sd_test.sv" `include “uvm\_sd\_tbtop.sv”

these are those files

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<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 19, 2018, 1:23pm UTC](https://verificationacademy.com/forums/t/uvm/34687/27 "2018-07-19T13:23:38Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/26):_

But I do not see the file ‘uvm\_sd\_allfiles.sv’ which is reported by the compiler.

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**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 20, 2018, 4:58am UTC](https://verificationacademy.com/forums/t/uvm/34687/28 "2018-07-20T04:58:34Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/27):_

that is the compile list file name. i have sent that too, saying //COMPILE LIST

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<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 20, 2018, 6:03am UTC](https://verificationacademy.com/forums/t/uvm/34687/29 "2018-07-20T06:03:23Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/28):_

Could you please put your code in an EDAplaygound example.

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**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 20, 2018, 7:14am UTC](https://verificationacademy.com/forums/t/uvm/34687/30 "2018-07-20T07:14:38Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/29):_

This is the eda link. Now i have got the output. But i dunno whether it is correct i.e is it compatible with the waveform??

> **[EDA Playground](https://www.edaplayground.com/x/5Zha)**
>
> Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

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<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 20, 2018, 11:51am UTC](https://verificationacademy.com/forums/t/uvm/34687/31 "2018-07-20T11:51:57Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/30):_

You had a few weaknesses in your testbench. The most important is a $sformatf you do not need (appears twice)  
use this uvm\_info instead of yours using the $sformatf which was not correct

```verilog
`uvm_info("VIF", {"virtual interface handle has been set for:",get_full_name(),".vif"},UVM_LOW)

```

Good simulators are reporting this weakness, but suppressing the error.

After a macro there is never a ‘;’  
And finally using

```verilog
`uvm_create

```

and

```verilog
`uvm_send

```

is not really useful. Use instead the

```verilog
`uvm_do

```

macro or work with

```verilog
start_item/finish_item

```

.

It is now working.  
See [(3) - EDA Playground](https://www.edaplayground.com/x/56ci)

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**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 23, 2018, 6:40am UTC](https://verificationacademy.com/forums/t/uvm/34687/32 "2018-07-23T06:40:35Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/31):_

Thank you so much for your help. It was very useful. Now i need to create a testcase with 1001 overlapping patterned input. But am not sure, how to give that. if i should give constraints, how to constraint it or is there any other i could give patterned inputs? Could you please help me out on this?

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**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 23, 2018, 7:02am UTC](https://verificationacademy.com/forums/t/uvm/34687/33 "2018-07-23T07:02:39Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/32):_

I don’t understand why you need 1001 input pattterns …  
But you can generate millions of patterns if needed by running an appropriate loop in your sequence.  
The common apprach is to add constraints to your seq item and you can also add constarints (so-called control knobs) to your sequences.  
I guess you need a certain number of sequences with different contraints to generate the patterns needed.

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<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 23, 2018, 7:16am UTC](https://verificationacademy.com/forums/t/uvm/34687/34 "2018-07-23T07:16:34Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/33):_

how to create loops using constraints? thats what exactly i need to know… I mean the syntax.

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**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 23, 2018, 7:30am UTC](https://verificationacademy.com/forums/t/uvm/34687/35 "2018-07-23T07:30:48Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/34):_

in the body method of your sequence you can implement a loop like this

```verilog
repeat (100)
  `uvm_do_with(req, with {your constraints;})

```

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**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 23, 2018, 7:44am UTC](https://verificationacademy.com/forums/t/uvm/34687/36 "2018-07-23T07:44:38Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/35):_

thank you so much. Thanks a lot.

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<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 23, 2018, 10:06am UTC](https://verificationacademy.com/forums/t/uvm/34687/37 "2018-07-23T10:06:47Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/36):_

could me suggest me few corner testcases for fsm sequence detector uvm verification??

---

<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 23, 2018, 11:16am UTC](https://verificationacademy.com/forums/t/uvm/34687/38 "2018-07-23T11:16:20Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/37):_

The absolut minimum is to verify all transitions from one state to another one.

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**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 23, 2018, 11:25am UTC](https://verificationacademy.com/forums/t/uvm/34687/39 "2018-07-23T11:25:33Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/38):_

That i have done already. Any other test cases??

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 23, 2018, 12:48pm UTC](https://verificationacademy.com/forums/t/uvm/34687/40 "2018-07-23T12:48:23Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm/34687/39):_

i want to check reset condition for my rtl. i.e while giving randomized inputs, i should apply reset in between, and all the fields should become zero when reset is 1. how to do that?

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