# UVM

**URL:** <https://verificationacademy.com/forums/t/uvm/34687>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [July 17, 2018, 5:47am UTC](https://verificationacademy.com/forums/t/uvm/34687 "2018-07-17T05:47:28Z")\
**Posts on this page:** 20\
**Page:** 1

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 17, 2018, 5:47am UTC](https://verificationacademy.com/forums/t/uvm/34687/1 "2018-07-17T05:47:28Z")

</div>

I am writing complete uvm testbench for fsm. My sequence isnt driving at all. I have completely checked my testbench and still not able to find whats wrong. Could you please help me out if I send you my code?

---

<div class="post-metadata">

**Author:** ![samy](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/54ee81/32.png) [@samy](https://verificationacademy.com/forums/u/samy)\
**Post date:** [July 17, 2018, 6:26am UTC](https://verificationacademy.com/forums/t/uvm/34687/2 "2018-07-17T06:26:21Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687):_

hi muthamizh ,

send me …

regards samy

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 17, 2018, 6:41am UTC](https://verificationacademy.com/forums/t/uvm/34687/3 "2018-07-17T06:41:03Z")

</div>

_In reply to [samy](https://verificationacademy.com/forums/t/uvm/34687/2):_

```verilog
//Sequence item class

class seq_item extends uvm_sequence_item;

//Randomizing the transaction fields

  rand bit in;
       bit out;
       bit [1:0] state;

//Object and utility macros

 `uvm_object_utils_begin(seq_item)
    `uvm_field_int(in,UVM_ALL_ON)
    `uvm_field_int(out,UVM_ALL_ON)
    `uvm_field_int(state,UVM_ALL_ON)
 `uvm_object_utils_end

//Constructor

 function new(string name="seq_item");
   super.new(name);
 endfunction

endclass

//Sequence class

class seq extends uvm_sequence#(seq_item);

//Utility macro

  `uvm_object_utils(seq)

//constructor

 function new(string name="seq");
   super.new(name);
 endfunction

//Body task

 virtual task body();

  repeat(40)
    begin
      `uvm_create(req);
       req.randomize();
      `uvm_send(req);
    end

 endtask

endclass

//Sequencer class

class sequencer extends uvm_sequencer#(seq_item);

//Utility macro

  `uvm_component_utils(sequencer)

//Constructor

 function new(string name="sequencer",uvm_component parent);
   super.new(name,parent);
 endfunction

endclass

//Driver class

class driver extends uvm_driver#(seq_item);

  virtual intf vif; //Virtual Interface handle

//Utility Macro

  `uvm_component_utils(driver)

//Constructor

  function new(string name="driver",uvm_component parent);
    super.new(name,parent);
  endfunction

//Build phase

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(uvm_config_db#(virtual intf)::get(this,"","vif",vif))
      `uvm_info("VIF",$sformatf("virtual interface handle has been set for:",get_full_name(),".vif"),UVM_LOW);
  endfunction

//Run phase

  virtual task run_phase(uvm_phase phase);
    reset;
    forever
      begin
        seq_item_port.get_next_item(req);
        drive();
        seq_item_port.item_done();
      end
 endtask

  task reset;
    wait(vif.rst);
     `uvm_info("INITIATION",$sformatf("Initialization has started"),UVM_LOW);
     vif.in=0;
    wait(!vif.rst);
     `uvm_info("DONE",$sformatf("Intialization is done"),UVM_LOW);
  endtask

//Drive task

  task drive();

     @(posedge vif.clk);
  
        vif.in<=req.in;
        req.state<=vif.state;
        req.out<=vif.out;
       `uvm_info("DRIVER",$sformatf("Input=%d\tState=%2b\tOutput=%d",vif.in,req.state,req.out),UVM_LOW);
        $display($time,"input=%d",vif.in,"State=%2b",vif.state,"Output=%d",vif.out);
  endtask

endclass

//Monitor class

class monitor extends uvm_monitor;

//Virtual Interface handle

  virtual intf vif;

  uvm_analysis_port #(seq_item) pkt_obtained_port;

//Handle to store transaction information

  seq_item trans;

//Utility Macro

  `uvm_component_utils(monitor);

//Constructor

 function new(string name="monitor",uvm_component parent);
   super.new(name,parent);
   trans=new;
   pkt_obtained_port=new("pkt_obtained_port",this);
 endfunction

//Build phase

 function void build_phase(uvm_phase phase);
   super.build_phase(phase);
 if(uvm_config_db#(virtual intf)::get(this,"","vif",vif))
     `uvm_info("VIF",$sformatf("virtual interface handle has been set for:",get_full_name(),".vif"),UVM_LOW);
 endfunction

//Run phase

 virtual task run_phase(uvm_phase phase);
    forever
      begin
        @(negedge vif.clk);

        trans.in=vif.in;
        trans.state=vif.state;
        trans.out=vif.out;
        `uvm_info("MONITOR",$sformatf("Input=%d\tState=%2b\tOutput=%d",trans.in,trans.state,trans.out),UVM_LOW);  
      end
       
        pkt_obtained_port.write(trans);

 endtask

endclass

```

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 17, 2018, 6:52am UTC](https://verificationacademy.com/forums/t/uvm/34687/4 "2018-07-17T06:52:06Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/3):_

```verilog
//Scoreboard class

class scoreboard extends uvm_scoreboard;

//Utility macro

`uvm_component_utils(scoreboard)

uvm_analysis_imp #(seq_item,scoreboard) pkt_obtained_export;

 seq_item trans;

//Constructor

 function new(string name="scoreboard",uvm_component parent);
   super.new(name,parent);
 endfunction

//Build phase

 function void build_phase(uvm_phase phase);
   super.build_phase(phase);
   pkt_obtained_export=new("pkt_obtained_export",this);
 endfunction

//Write function

 virtual function void write(seq_item pkt);
   $display("Packets received");
   pkt.print();

 endfunction
endclass

//Agent class

class agent extends uvm_agent;
  
  sequencer seqcr;
  driver dri;
  monitor moni;

//Utility macro 

 `uvm_component_utils(agent)

//Constructor

 function new(string name, uvm_component parent);
   super.new(name,parent);
 endfunction

//Build phase

 function void build_phase(uvm_phase phase);
   super.build_phase(phase);
   if(get_is_active()==UVM_ACTIVE)
     begin
       dri=driver::type_id::create("dri",this);
       seqcr=sequencer::type_id::create("seqcr",this);
     end
       moni=monitor::type_id::create("moni",this);
 endfunction

//Connect phase

 function void connect_phase(uvm_phase phase);
   super.connect_phase(phase);
   if(get_is_active()==UVM_ACTIVE) 
     begin
dri.seq_item_port.connect(seqcr.seq_item_export);
     end
 endfunction

endclass

//Environment class

class environment extends uvm_env;

  agent agnt;
  scoreboard sb;
 
//Utility Macro

  `uvm_component_utils(environment)

//Constructor

 function new(string name="environment",uvm_component parent);
   super.new(name,parent);
 endfunction

//Build phase

 function void build_phase(uvm_phase phase);
   super.build_phase(phase);
   agnt=agent::type_id::create("agnt",this);
   sb=scoreboard::type_id::create("sb",this);
 endfunction

//Connect phase
 function void connect_phase(uvm_phase phase);
   super.connect_phase(phase);
   agnt.moni.pkt_obtained_port.connect(sb.pkt_obtained_export);
 endfunction

endclass

//Test class

class test extends uvm_test;

//Utility Macro

 `uvm_component_utils(test)

    environment env;
    seq seq1;

//Constructor

 function new(string name="test",uvm_component parent);
   super.new(name,parent);
 endfunction

//Build phase

 function void build_phase(uvm_phase phase);
   super.build_phase(phase);
   env=environment::type_id::create("env",this);
   seq1=seq::type_id::create("seq1",this);
 endfunction

//Run phase

 task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    seq1.start(env.agnt.seqcr);
    phase.drop_objection(this);
 endtask

endclass

`include "uvm_sd_test.sv"

module tb_top;

  bit clk;
  bit rst;
  
//clock generation

  always #2 clk=~clk;

//reset generation

initial
  begin
    rst=1;
    #2 rst=0;
  end

//Interface instance

  intf vif(clk,rst);

//DUT instance

  fsm1 DUT(.clk(vif.clk),
           .rst(vif.rst),
           .in(vif.in),
           .out(vif.out),
           .state(vif.state));

//Setting configuration database
 initial
   begin
     uvm_config_db#(virtual intf)::set(uvm_root::get(),"*","vif",vif);
     $dumpfile("dump.vcd");
     $dumpvars;
   end

 initial
   begin
     run_test("test");
   end

endmodule

interface intf(input clk,rst);

  logic [1:0] state; //Indicates the 2 bit states of transition in the fsm
  logic in;
  logic out;
 
endinterface

RTL

//RTL for FSM 1001 MEALY OVERLAPPING SEQUENCE DETECTOR
//=======================================================

//Module for the input and output ports 

module fsm1(clk,rst,in,out,state);

  input clk,rst,in;
  output out;
  output [1:0] state;
  reg [1:0] state,nextstate;
  reg out;

//Clock block for resetting and state transition

always @ (posedge clk)
  begin
    if(rst)
      begin

        state=2'b00; //The state goes to reset state when reset is 1

      end
    else
      begin

        state=nextstate; //next state becomes the current state when reset is 0

      end
  end

//Always block for state transition

always @(state or in)
 begin

   case({state,in})

     3'b000:begin
       nextstate<=2'b00;
       out<=0;
     end

     3'b001:begin
       nextstate<=2'b01;
       out<=0;
     end

     3'b010:begin
       nextstate<=2'b10;
       out<=0;
     end

     3'b011: begin
       nextstate<=2'b01;
       out<=0;
     end

     3'b100:begin
       nextstate<=2'b11;
       out<=0;
     end
  3'b101:begin
       nextstate<=2'b01;
       out<=0;
     end

     3'b110:begin
       nextstate<=2'b00;
       out<=0;
     end

     3'b111: begin
       nextstate<=2'b01;
       out<=1; //When the sequence is detected output becomes 1
     end

endcase
end
endmodule

```

COMPILE LIST

import uvm\_pkg::\*;  
`include “uvm\_macros.svh”

`include "fsm1.sv" `include “uvm\_sd\_interface.sv”  
`include "uvm_sd_seq_item.sv" `include “uvm\_sd\_sequence.sv”  
`include "uvm_sd_sequencer.sv" `include “uvm\_sd\_driver.sv”  
`include "uvm_sd_monitor.sv" `include “uvm\_sd\_agent.sv”  
`include "uvm_sd_scoreboard.sv" `include “uvm\_sd\_environment.sv”  
`include “uvm\_sd\_tbtop.sv”

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 17, 2018, 6:53am UTC](https://verificationacademy.com/forums/t/uvm/34687/5 "2018-07-17T06:53:28Z")

</div>

_In reply to [samy](https://verificationacademy.com/forums/t/uvm/34687/4):_

> _In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/4):_  
> hi muthamizh ,  
> send me …  
> regards samy

I have sent the complete code along with rtl. It will be very helpful if you could find out whats wrong and help me out

---

<div class="post-metadata">

**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [July 17, 2018, 12:50pm UTC](https://verificationacademy.com/forums/t/uvm/34687/6 "2018-07-17T12:50:33Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/5):_

Can you be more descriptive beyond “My sequence isn’t driving at all”? What output are you seeing? What output do you expect to see? What do you think the issue is? An output transcript with the error(s) you are seeing is very helpful.

One simple issue is that your reset isn’t long enough. Try changing it from #2 to #20.

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 5:05am UTC](https://verificationacademy.com/forums/t/uvm/34687/7 "2018-07-18T05:05:18Z")

</div>

_In reply to [cgales](https://verificationacademy.com/forums/t/uvm/34687/6):_

> _In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/6):_  
> Can you be more descriptive beyond “My sequence isn’t driving at all”? What output are you seeing? What output do you expect to see? What do you think the issue is? An output transcript with the error(s) you are seeing is very helpful.  
> One simple issue is that your reset isn’t long enough. Try changing it from #2 to #20.

```
             106input=1State=xxOutput=x

```

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 106: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 110: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 110input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 110: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 114: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 114input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 114: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 118: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 118input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 118: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 122: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 122input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 122: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 126: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 126input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 126: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 130: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 130input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 130: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 134: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 134input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 134: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 138: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 138input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 138: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 142: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 142input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 142: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 146: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 146input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 146: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 150: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 150input=0State=xxOutput=x

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 5:08am UTC](https://verificationacademy.com/forums/t/uvm/34687/8 "2018-07-18T05:08:21Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/7):_

> _In reply to [cgales](https://verificationacademy.com/forums/t/uvm/34687/7):_  
> 106input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 106: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 110: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 110input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 110: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 114: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 114input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 114: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 118: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 118input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 118: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 122: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 122input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 122: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 126: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 126input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 126: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 130: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 130input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 130: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 134: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# 134input=1State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 134: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 138: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 138input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 138: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 142: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 142input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 142: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 146: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 146input=0State=xxOutput=x

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 146: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 150: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# 150input=0State=xxOutput=x

This is the output am getting now. but if the signals are driven, there should be state transition happening in my output. if you see my dut rtl, u could understand the way state transition happens. And regarding output, it should become 1 when the sequence 1001 is detected. In the waveform also state and output do not show at all. This is my problem.

---

<div class="post-metadata">

**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\
**Post date:** [July 18, 2018, 5:16am UTC](https://verificationacademy.com/forums/t/uvm/34687/9 "2018-07-18T05:16:16Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/8):_

yes, Reset isn’t long enough. here i am attaching code after increasing reset duration to 20 and it is working as per your expectations.

Link:-

> **[EDA Playground](https://www.edaplayground.com/x/4QCB)**
>
> Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

Regards,  
Mitesh

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 5:36am UTC](https://verificationacademy.com/forums/t/uvm/34687/10 "2018-07-18T05:36:27Z")

</div>

_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm/34687/9):_

Yes its working… Thanks a lot… but still the driver doesnt change and the scoreboard isnt displayed at all… what should i do for this?

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 5:43am UTC](https://verificationacademy.com/forums/t/uvm/34687/11 "2018-07-18T05:43:38Z")

</div>

_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm/34687/10):_

> _In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/10):_  
> yes, Reset isn’t long enough. here i am attaching code after increasing reset duration to 20 and it is working as per your expectations.  
> Link:-  
> [Edit code - EDA Playground](https://www.edaplayground.com/x/4QCB)  
> Regards,  
> Mitesh

really, thanks a lot for helping me out. I have been checking this for the past 3 days. It will be very helpful if you are able to help me out with driver and scoreboard. Thank you again

---

<div class="post-metadata">

**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\
**Post date:** [July 18, 2018, 5:59am UTC](https://verificationacademy.com/forums/t/uvm/34687/12 "2018-07-18T05:59:25Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/11):_

Because, write method from monitor is called outside the forever begin. ideally when, you sampled anything from interface it should be write to analysis port.

please find the link, it is showing packet received messages from scoreboard.  
Link:-

> **[EDA Playground](https://www.edaplayground.com/x/4QCB)**
>
> Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 6:19am UTC](https://verificationacademy.com/forums/t/uvm/34687/13 "2018-07-18T06:19:03Z")

</div>

_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm/34687/12):_

> _In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/12):_  
> Because, write method from monitor is called outside the forever begin. ideally when, you sampled anything from interface it should be write to analysis port.  
> please find the link, it is showing packet received messages from scoreboard.  
> Link:-  
> [Edit code - EDA Playground](https://www.edaplayground.com/x/4QCB)

Thank you so much. It is very very helpful. Thanks a lot

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 7:46am UTC](https://verificationacademy.com/forums/t/uvm/34687/14 "2018-07-18T07:46:56Z")

</div>

_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm/34687/13):_

> _In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/13):_  
> Because, write method from monitor is called outside the forever begin. ideally when, you sampled anything from interface it should be write to analysis port.  
> please find the link, it is showing packet received messages from scoreboard.  
> Link:-  
> [Edit code - EDA Playground](https://www.edaplayground.com/x/4QCB)

The input of driver and monitor changes. Could you please help me out with that?

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 7:47am UTC](https://verificationacademy.com/forums/t/uvm/34687/15 "2018-07-18T07:47:35Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/14):_

I am also trying to correct it. Still a help would be supportive.

---

<div class="post-metadata">

**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\
**Post date:** [July 18, 2018, 8:08am UTC](https://verificationacademy.com/forums/t/uvm/34687/16 "2018-07-18T08:08:33Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/15):_

Can you please elaborate more? which inputs are changes ? i didnt get your question.

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 8:53am UTC](https://verificationacademy.com/forums/t/uvm/34687/17 "2018-07-18T08:53:13Z")

</div>

_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm/34687/16):_

UVM\_INFO uvm\_sd\_driver.sv(59) @ 38: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=11 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 40: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(36) @ 40: uvm\_test\_top.env.sb [SB] Sequence is not yet started and so stays in reset state itself

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 42: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 44: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(40) @ 44: uvm\_test\_top.env.sb [SB] Sequence is started and so it goes to the next state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(41) @ 44: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 46: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 48: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(45) @ 48: uvm\_test\_top.env.sb [SB] Sequence continues and it goes to next state 10

# UVM\_INFO uvm\_sd\_scoreboard.sv(46) @ 48: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 50: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 52: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=10 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(60) @ 52: uvm\_test\_top.env.sb [SB] Sequence is broken and so goes to state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(61) @ 52: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 54: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=10 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 56: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(50) @ 56: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(51) @ 56: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 58: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=01 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 60: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 8:55am UTC](https://verificationacademy.com/forums/t/uvm/34687/18 "2018-07-18T08:55:00Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/17):_

> _In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm/34687/17):_  
> UVM\_INFO uvm\_sd\_driver.sv(59) @ 38: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=11 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 40: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=00 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(36) @ 40: uvm\_test\_top.env.sb [SB] Sequence is not yet started and so stays in reset state itself

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 42: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 44: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(40) @ 44: uvm\_test\_top.env.sb [SB] Sequence is started and so it goes to the next state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(41) @ 44: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 46: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=00 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 48: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(45) @ 48: uvm\_test\_top.env.sb [SB] Sequence continues and it goes to next state 10

# UVM\_INFO uvm\_sd\_scoreboard.sv(46) @ 48: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 50: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 52: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=10 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(60) @ 52: uvm\_test\_top.env.sb [SB] Sequence is broken and so goes to state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(61) @ 52: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 54: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=10 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 56: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(50) @ 56: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(51) @ 56: uvm\_test\_top.env.sb Got expected response

# ----------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_driver.sv(59) @ 58: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=01 Output=0

# UVM\_INFO uvm\_sd\_monitor.sv(48) @ 60: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

Im getting output like this now. the driver and monitor should show the same output. But only the monitor shows the correct output. There is problem with driver clock i guess. but I am not able to identify it. Could you please help me with this?

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 10:14am UTC](https://verificationacademy.com/forums/t/uvm/34687/19 "2018-07-18T10:14:28Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/18):_

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 94: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(44) @ 94: uvm\_test\_top.env.sb [SB] Sequence is started and so it goes to the next state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(45) @ 94: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 94: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 98: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(49) @ 98: uvm\_test\_top.env.sb [SB] Sequence continues and it goes to next state 10

# UVM\_INFO uvm\_sd\_scoreboard.sv(50) @ 98: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 98: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 102: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=10 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(64) @ 102: uvm\_test\_top.env.sb [SB] Sequence is broken and so goes to state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(65) @ 102: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 102: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=10 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 106: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(49) @ 106: uvm\_test\_top.env.sb [SB] Sequence continues and it goes to next state 10

# UVM\_INFO uvm\_sd\_scoreboard.sv(50) @ 106: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 106: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 110: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=10 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(64) @ 110: uvm\_test\_top.env.sb [SB] Sequence is broken and so goes to state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(65) @ 110: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 110: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=10 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 114: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 114: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 114: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 114: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 118: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 118: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 118: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 118: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 122: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 122: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 122: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 122: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 126: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 126: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 126: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 126: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

---

<div class="post-metadata">

**Author:** ![Muthamizh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/f1d935/32.png) [@Muthamizh](https://verificationacademy.com/forums/u/Muthamizh)\
**Post date:** [July 18, 2018, 10:15am UTC](https://verificationacademy.com/forums/t/uvm/34687/20 "2018-07-18T10:15:45Z")

</div>

_In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/19):_

> _In reply to [Muthamizh](https://verificationacademy.com/forums/t/uvm/34687/19):_

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 94: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=00 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(44) @ 94: uvm\_test\_top.env.sb [SB] Sequence is started and so it goes to the next state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(45) @ 94: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 94: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=00 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 98: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(49) @ 98: uvm\_test\_top.env.sb [SB] Sequence continues and it goes to next state 10

# UVM\_INFO uvm\_sd\_scoreboard.sv(50) @ 98: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 98: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 102: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=10 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(64) @ 102: uvm\_test\_top.env.sb [SB] Sequence is broken and so goes to state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(65) @ 102: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 102: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=10 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 106: uvm\_test\_top.env.agnt.moni [MONITOR] Input=0 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(49) @ 106: uvm\_test\_top.env.sb [SB] Sequence continues and it goes to next state 10

# UVM\_INFO uvm\_sd\_scoreboard.sv(50) @ 106: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 106: uvm\_test\_top.env.agnt.dri [DRIVER] Input=0 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 110: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=10 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(64) @ 110: uvm\_test\_top.env.sb [SB] Sequence is broken and so goes to state 01

# UVM\_INFO uvm\_sd\_scoreboard.sv(65) @ 110: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 110: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=10 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 114: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 114: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 114: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 114: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 118: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 118: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 118: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 118: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 122: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 122: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 122: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 122: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

# UVM\_INFO uvm\_sd\_monitor.sv(49) @ 126: uvm\_test\_top.env.agnt.moni [MONITOR] Input=1 State=01 Output=0

# Packets received

# UVM\_INFO uvm\_sd\_scoreboard.sv(54) @ 126: uvm\_test\_top.env.sb [SB] Sequence is broken and so stays in 01 state itself

# UVM\_INFO uvm\_sd\_scoreboard.sv(55) @ 126: uvm\_test\_top.env.sb Got expected response

# UVM\_INFO uvm\_sd\_driver.sv(58) @ 126: uvm\_test\_top.env.agnt.dri [DRIVER] Input=1 State=01 Output=0

# ------------------------------------------------------------------------------------------------------------------------

I have corrected it to this extent. But the driver is displayed after monitor and scoreboard. How to make driver to display before monitor and scoreboard?

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