# UVM utility macros

**URL:** <https://verificationacademy.com/forums/t/uvm-utility-macros/34555>\
**Category:** UVM\
**Tags:** UVM, field-macros\
**Created:** [June 8, 2018, 12:05pm UTC](https://verificationacademy.com/forums/t/uvm-utility-macros/34555 "2018-06-08T12:05:39Z")\
**Posts on this page:** 1\
**Showing post:** 5

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**Author:** ![verif\_learner1](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/v/7993a0/32.png) [@verif\_learner1](https://verificationacademy.com/forums/u/verif_learner1)\
**Post date:** [June 22, 2018, 3:31pm UTC](https://verificationacademy.com/forums/t/uvm-utility-macros/34555/5 "2018-06-22T15:31:01Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/uvm-utility-macros/34555/4):_

Tom, Dave,  
I am opening this post again as I am still have some questions.

1. when you say, just use

```verilog
`uvm_object_utils(simple_item)

```

Does it mean that we don’t need to use:

```verilog
`uvm_field_int(addr, UVM_ALL_ON)

```

I am under the impression that these are needed in order to automate basic operations in a component and item (e.g. copy, print etc.)

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