# Uvm\_sequence randomization

**URL:** <https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553>\
**Category:** UVM\
**Tags:** UVM, uvm\_sequence, randomization\
**Created:** [April 20, 2023, 10:02am UTC](https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553 "2023-04-20T10:02:39Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [April 21, 2023, 12:53pm UTC](https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553/4 "2023-04-21T12:53:42Z")

</div>

_In reply to [Boogeyman](https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553/3):_

If you add a little more code, you can create a self-contained example which demonstrates your issue.

Your issue is that you have variables with the same name in both trans\_seq and write\_seq. Section 18.7 of the LRM explains how to differentiate between a variable that is local to the class calling randomize() and a variable that is local to the class being randomized. You want to use the qualifier “local::” and not “this.”

```verilog

import uvm_pkg::*;
`include "uvm_macros.svh"

class write_seq extends uvm_sequence #(uvm_sequence_item);
  `uvm_object_utils(write_seq)
  
  rand bit[31:0] write_data;
  rand bit[31:0] address;
  
  function new(string name="write_seq");
    super.new(name);
  endfunction
  
  task body();
    `uvm_info(get_name(), $sformatf("write_seq has address: %0h and write_data: %0h", address, write_data), UVM_MEDIUM);
  endtask
endclass : write_seq
 
class trans_seq extends uvm_sequence #(uvm_sequence_item);
  `uvm_object_utils(trans_seq)
 
  function new(string name = "trans_seq");
    super.new(name);
  endfunction : new

  rand bit[31:0] write_data;
  rand bit[31:0] address; 
 
  task body();
    write_seq write_seq_incorrect_randomization = write_seq::type_id::create("write_seq_incorrect_randomization");
    write_seq write_seq_correct_randomization = write_seq::type_id::create("write_seq_correct_randomization");

    `uvm_info(get_name(), $sformatf("trans_seq has address: %0h and write_data: %0h", address, write_data), UVM_MEDIUM);
    
    if (!write_seq_incorrect_randomization.randomize with {write_data == this.write_data;
                                                           address == this.address;}) begin
      `uvm_fatal("RNDERR", "Unable to randomize write_seq_incorrect_randomization");
    end
    write_seq_incorrect_randomization.start(null);
    
    if (!write_seq_correct_randomization.randomize with {write_data == local::write_data;
                                                         address == local::address;}) begin
      `uvm_fatal("RNDERR", "Unable to randomize write_seq_correct_randomization");
    end
    write_seq_correct_randomization.start(null);
    
  endtask : body
endclass : trans_seq

class my_test extends uvm_test;
  `uvm_component_utils(my_test);
  
  function new(string name="my_test", uvm_component parent = null);
    super.new(name,parent);
  endfunction
  
  task run_phase(uvm_phase phase);
    trans_seq test_seq = trans_seq::type_id::create("test_seq");
    repeat (10) begin
      if (!test_seq.randomize()) begin
        `uvm_fatal("RNDERR", "Unable to randomize trans_seq");
      end
      test_seq.start(null);
    end
  endtask
endclass

module testbench();
  initial begin
    run_test("my_test");
  end
endmodule

```

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