# Uvm\_sequence randomization

**URL:** <https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553>\
**Category:** UVM\
**Tags:** UVM, uvm\_sequence, randomization\
**Created:** [April 20, 2023, 10:02am UTC](https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553 "2023-04-20T10:02:39Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![Boogeyman](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/b/b38774/32.png) [@Boogeyman](https://verificationacademy.com/forums/u/Boogeyman)\
**Post date:** [April 21, 2023, 5:08am UTC](https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553/3 "2023-04-21T05:08:14Z")

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_In reply to [cgales](https://verificationacademy.com/forums/t/uvm-sequence-randomization/41553/2):_

Hi Cgales,

Thanks for the comment. In the below code, whatever randomized in trans\_seq will be passed to write\_seq right. But, while executing this code, I observed that, write\_seq.write\_data and write\_seq.address has different data.

Note : Both are started with p\_sequencer.

```verilog
class write_seq extends uvm_sequence #(uvm_sequence_item);
  `uvm_object_utils(write_seq)
  `uvm_declare_p_sequencer(virtual_sequencer) 
   rand bit[31:0] write_data;
   rand bit[31:0] address;
endclass : write_seq

class trans_seq extends uvm_sequence #(uvm_sequence_item);
  `uvm_object_utils(trans_seq)
  `uvm_declare_p_sequencer(virtual_sequencer) 

  function new(string name = "trans_seq");
    super.new(name);
  endfunction : new

   rand bit[31:0] write_data;
   rand bit[31:0] address; 
 
   write_seq wr_seq;

   extern virtual task body();
endclass : trans_seq

task trans_seq::body();
    wr_seq = write_seq::type_id::create("wr_seq"); 
    wr_seq.randomize with {write_data == this.write_data;
                           address == this.address;};
    wr_seq.start(p_sequencer);
endtask : body

```

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