# UVM Phase Synchronization

**URL:** <https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [December 22, 2017, 11:09am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852 "2017-12-22T11:09:24Z")\
**Posts on this page:** 1\
**Showing post:** 6

<div class="post-metadata">

**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\
**Post date:** [December 26, 2017, 4:16am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/6 "2017-12-26T04:16:09Z")

</div>

_In reply to [sharvil111](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/5):_

Thanks sharvil111 and chr\_sue for response.  
i used same code as mentioned by you. but not getting expected output. here i am attaching code. please let me know if i misunderstood, i am using VCS tool for compile and run the simulation.

/\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/  
class driver extends uvm\_component;  
`uvm\_component\_utils(driver)  
function new(string name = “driver”,uvm\_component parent = null);  
super.new(name,parent);  
endfunction

```
task reset_phase(uvm_phase phase);
  phase.raise_objection(this);
  #5;
  $display($time,"\tdriver: reset phase ended");
  phase.drop_objection(this);
endtask

task main_phase(uvm_phase phase);
  phase.raise_objection(this);
  phase.drop_objection(this);
endtask

```

endclass  
/\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/  
class monitor extends uvm\_component;  
uvm\_phase p;

```
`uvm_component_utils(monitor)
function new(string name = "monitor",uvm_component parent = null);
  super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
  p = phase.find_by_name("main",0);
  if(p == null) $display("P found null");
endfunction

task run_phase(uvm_phase phase);
  phase.raise_objection(this);
  p.wait_for_state(UVM_PHASE_STARTED);
  $display($time,"\tMonitor unblocked");
  phase.drop_objection(this);
endtask

```

endclass

/\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/  
class test extends uvm\_test;  
`uvm\_component\_utils(test)

```
function new (string name, uvm_component parent);
  super.new(name, parent);
endfunction

driver drv;
monitor mon;

function void build_phase(uvm_phase phase);
  uvm_config_db#(int)::set(this, "drv", "delay", 10);
  uvm_config_db#(int)::set(this, "mon", "delay", 100);
  
  drv = driver::type_id::create("drv", this);
  mon = monitor::type_id::create("mon", this);
  
endfunction

function void start_of_simulation_phase(uvm_phase phase);
  //this.set_report_verbosity_level_hier(UVM_HIGH);
endfunction

```

endclass

/\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/  
module top;

import uvm\_pkg::\*;

initial  
run\_test(“test”);

endmodule  
/\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/

/\*  
Output:-

(Specify +UVM\_NO\_RELNOTES to turn off this notice)

UVM\_INFO @ 0: reporter [RNTST] Running test test…  
0 Monitor unblocked  
UVM\_INFO /apps/vcsmx/etc/uvm-1.2/src/base/uvm\_objection.svh(1270) @ 0: reporter [TEST\_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase  
5 driver: reset phase ended  
UVM\_INFO /apps/vcsmx/etc/uvm-1.2/src/base/uvm\_report\_server.svh(847) @ 5: reporter [UVM/REPORT/SERVER]

\*/

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