# UVM Phase Synchronization **URL:** \ **Category:** UVM\ **Tags:** UVM\ **Created:** [December 22, 2017, 11:09am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852 "2017-12-22T11:09:24Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\ **Post date:** [December 22, 2017, 11:09am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/1 "2017-12-22T11:09:24Z")
Hello, ``` I am having question related to phase synchronization in uvm. let me explain by code. ``` 1. my driver class has following phases. build\_phase, reset\_phase, configure\_phase, main\_phase ```verilog class my_driver extends uvm_driver; function new ******************** function build_phase(uvm_phase phase); // Necessary logic endfunction : build_phase task reset_phase(uvm_phase phase); // Necessary logic endtask : reset_phase task configure_phase(uvm_phase phase); // Necessary logic endtask : configure_phase task main_phase(uvm_phase phase); // Necessary logic endtask : main_phase endclass : my_driver ``` 1. my monitor class has following phases. build\_phase and run\_phase. ```verilog class my_monitor extends uvm_monitor; function new ******************** function build_phase(uvm_phase phase); // Necessary logic endfunction : build_phase task run_phase(uvm_phase phase); // Necessary logic /* I want to add logic here, which can detect uvm phases of other class,*/ endtask : run_phase endclass : my_monitor ``` i want to synchronize main\_phase of driver class with run\_phase of monitor class. my requirement is [b]run\_phase of monitor class only start executing when main\_phase of driver class is started. is there any mechanism for such issue in uvm? or is there any mechanism by which i can know which phase is executing? Please let me know if more details are required from my side. Thanks in advance. Mitesh N.Patel ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [December 22, 2017, 12:11pm UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/2 "2017-12-22T12:11:24Z")
_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852):_ You want to mix the run-subphases, like reset\_phase, configure\_phase etc., with the run\_phase. This is a bad approach. If you have reasons to deal with the sub-phases Of UVM you should do this in all components. The best solution is to use in your monitor main\_phase instead of run\_phase. But I’m not sure that you really need the sub-phases of the run\_phase. The key question is, what do you want to do in these phases. ---
**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\ **Post date:** [December 25, 2017, 12:19pm UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/3 "2017-12-25T12:19:21Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/2):_ Hi chr\_sue, ``` Thanks for response, i know that this approach is not recommended. but in my environment, developed VIPs are having run_phases and i have to reuse that VIPs. and i can not simply use run_phase, i have to compulsory use, 13 phases parallel with run_phase. so is there any mechanism in UVM, by which i can control over above situation? ``` Thanks in Advance Mitesh N. Patel ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [December 25, 2017, 6:28pm UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/4 "2017-12-25T18:28:05Z")
_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/3):_ Do you really need the reset\_phase, configure\_phase etc.? Could you please explain why? You can perform a reset and the configuration using reset sequences and configuration sequences while running the run\_phase only. ---
**Author:** ![sharvil111](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/sharvil111/32/3790_2.png) [@sharvil111](https://verificationacademy.com/forums/u/sharvil111)\ **Post date:** [December 26, 2017, 3:40am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/5 "2017-12-26T03:40:28Z")
As suggested by _chr\_sue_, the usage of **mixed-phases is not recommended practice**. Still if you have constraints of **multiple phase usage** , then **you can make use of _wait\_for\_state_ API of UVM phase**. The _uvm\_phase_ class provides the “_wait\_for\_state_” task to **wait till a particular state of phase is reached**. All you need to do is **get a handle of implementation of a phase and call the API**. In the _build\_phase_ of _monitor_, **get the handle of _main\_phase_ implementation**. Thereafter, in the _run_ phase, **call the wait task to wait till _driver_ reaches main phase**. ```verilog // Get handle of main phase in monitor uvm_phase p; p = phase.find_by_name("main",0); // find_by_name prototype // extern function uvm_phase find_by_name(string name, bit stay_in_scope=1); // Call wait task in monitor run phase p.wait_for_state(UVM_PHASE_STARTED); // wait_for_state prototype // extern task wait_for_state(uvm_phase_state state, uvm_wait_op op=UVM_EQ); ``` Note that this works in a single phase domain, I have not tested it across multiple domains. Following is an example of how the wait task is invoked to block the monitor. ```verilog class driver extends uvm_component; `uvm_component_utils(driver) function new(string name = "driver",uvm_component parent = null); super.new(name,parent); endfunction task reset_phase(uvm_phase phase); phase.raise_objection(this); #5; $display($time,"\tdriver: reset phase ended"); phase.drop_objection(this); endtask task main_phase(uvm_phase phase); phase.raise_objection(this); phase.drop_objection(this); endtask endclass class monitor extends uvm_component; uvm_phase p; `uvm_component_utils(monitor) function new(string name = "monitor",uvm_component parent = null); super.new(name,parent); endfunction function void build_phase(uvm_phase phase); p = phase.find_by_name("main",0); if(p == null) $display("P found null"); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); p.wait_for_state(UVM_PHASE_STARTED); $display($time,"\tMonitor unblocked"); phase.drop_objection(this); endtask endclass // Output UVM_INFO @ 0: reporter [RNTST] Running test test... 5 driver: reset phase ended 5 Monitor unblocked UVM_INFO /apps/vcsmx/etc/uvm-1.1/src/base/uvm_objection.svh(1267) @ 5: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase ``` For more information refer to [uvm\_phase.svh](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/src/base/uvm_phase.svh) and [uvm\_phase singletons question](http://forums.accellera.org/topic/1769-uvm-phase-singletons/). [This blog post](http://blog.verificationgentleman.com/2014/04/uvm-drain-time-old-fashioned-way.html) might also be useful. ---
**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\ **Post date:** [December 26, 2017, 4:16am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/6 "2017-12-26T04:16:09Z")
_In reply to [sharvil111](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/5):_ Thanks sharvil111 and chr\_sue for response. i used same code as mentioned by you. but not getting expected output. here i am attaching code. please let me know if i misunderstood, i am using VCS tool for compile and run the simulation. /\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/ class driver extends uvm\_component; `uvm\_component\_utils(driver) function new(string name = “driver”,uvm\_component parent = null); super.new(name,parent); endfunction ``` task reset_phase(uvm_phase phase); phase.raise_objection(this); #5; $display($time,"\tdriver: reset phase ended"); phase.drop_objection(this); endtask task main_phase(uvm_phase phase); phase.raise_objection(this); phase.drop_objection(this); endtask ``` endclass /\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/ class monitor extends uvm\_component; uvm\_phase p; ``` `uvm_component_utils(monitor) function new(string name = "monitor",uvm_component parent = null); super.new(name,parent); endfunction function void build_phase(uvm_phase phase); p = phase.find_by_name("main",0); if(p == null) $display("P found null"); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); p.wait_for_state(UVM_PHASE_STARTED); $display($time,"\tMonitor unblocked"); phase.drop_objection(this); endtask ``` endclass /\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/ class test extends uvm\_test; `uvm\_component\_utils(test) ``` function new (string name, uvm_component parent); super.new(name, parent); endfunction driver drv; monitor mon; function void build_phase(uvm_phase phase); uvm_config_db#(int)::set(this, "drv", "delay", 10); uvm_config_db#(int)::set(this, "mon", "delay", 100); drv = driver::type_id::create("drv", this); mon = monitor::type_id::create("mon", this); endfunction function void start_of_simulation_phase(uvm_phase phase); //this.set_report_verbosity_level_hier(UVM_HIGH); endfunction ``` endclass /\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/ module top; import uvm\_pkg::\*; initial run\_test(“test”); endmodule /\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/ /\* Output:- (Specify +UVM\_NO\_RELNOTES to turn off this notice) UVM\_INFO @ 0: reporter [RNTST] Running test test… 0 Monitor unblocked UVM\_INFO /apps/vcsmx/etc/uvm-1.2/src/base/uvm\_objection.svh(1270) @ 0: reporter [TEST\_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase 5 driver: reset phase ended UVM\_INFO /apps/vcsmx/etc/uvm-1.2/src/base/uvm\_report\_server.svh(847) @ 5: reporter [UVM/REPORT/SERVER] \*/ ---
**Author:** ![sharvil111](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/sharvil111/32/3790_2.png) [@sharvil111](https://verificationacademy.com/forums/u/sharvil111)\ **Post date:** [December 26, 2017, 4:48am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/7 "2017-12-26T04:48:34Z")
_In reply to [mitesh.patel](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/6):_ The same code works for me. It blocks monitor for 5ns. ```verilog UVM_INFO @ 0: reporter [RNTST] Running test test... 5 driver: reset phase ended 5 Monitor unblocked UVM_INFO /apps/vcsmx/etc/uvm-1.1/src/base/uvm_objection.svh(1267) @ 5: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase ``` Please find the code at [Edit code - EDA Playground](https://www.edaplayground.com/x/29xA) . Note that I am also using VCS with UVM-1.1d (and UVM-1.2). ---
**Author:** ![mitesh.patel](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/7cd45c/32.png) [@mitesh.patel](https://verificationacademy.com/forums/u/mitesh.patel)\ **Post date:** [December 26, 2017, 5:05am UTC](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/8 "2017-12-26T05:05:44Z")
_In reply to [sharvil111](https://verificationacademy.com/forums/t/uvm-phase-synchronization/33852/7):_ Yeah sharvil111, It is working fine. Thanks Mitesh N. Patel