# UVM\_ERROR

**URL:** <https://verificationacademy.com/forums/t/uvm-error/33733>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [November 21, 2017, 7:00am UTC](https://verificationacademy.com/forums/t/uvm-error/33733 "2017-11-21T07:00:23Z")\
**Posts on this page:** 20\
**Page:** 1

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 21, 2017, 7:00am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/1 "2017-11-21T07:00:23Z")

</div>

Hi,

I’m getting a error for following code of uvm\_driver,  
**Can you help on this**.

```verilog
  begin
      sequence_item req;
      @ (MDPORT.cb);
      seq_item_port.get_next_item(req); // Gets the sequence_item 
      MDPORT.cb.lframe <= 1; // Start of frame
      for(int i = 0; i < 8; i++) begin // Send nibbles
        @(MDPORT.cb);
        MDPORT.cb.data <= req.data[3:0];
        req.data = req.data >> 4;
      end
      MDPORT.cb.lframe <= 0; // End of frame
      seq_item_port.item_done(); // Indicates that the sequence_item has been consumed
    end

```

**ERROR** :Unresolved hierarchical reference to “seq\_item\_port.get\_next\_item./0/” from module “\package my\_pkg.ac\_lpc\_driver” (module not found).

Thanks,  
Prawin

---

<div class="post-metadata">

**Author:** ![user60](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user60/32/1096_2.png) [@user60](https://verificationacademy.com/forums/u/user60)\
**Post date:** [November 21, 2017, 7:48am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/2 "2017-11-21T07:48:40Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733):_

Can you how you’ve declared your driver? Also do you use any special UVM library version or standard?

Srini

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 21, 2017, 8:05am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/3 "2017-11-21T08:05:42Z")

</div>

_In reply to [Srini @ CVCblr.com](https://verificationacademy.com/forums/t/uvm-error/33733/2):_

```verilog
class ac_lpc_driver extends uvm_driver #(sequence_item);

//uvm_macros

//sequence_item req;

// interface declaration

 uvm_analysis_port#(sequence_item)seq_item_port;

function new(string name = "ac_lpc_driver", uvm_component parent = null);
  super.new(name, parent);
  seq_item_port=new("port",this);
endfunction
 
//build_phase
  
task run_phase(uvm_phase phase);

  // Default conditions:
  MDPORT.cb.lframe <= 0;
  MDPORT.cb.data <= 0;
  fork
  forever
    begin
      sequence_item req;
      @ (MDPORT.cb);
      seq_item_port.get_next_item(req); // Gets the sequence_item 
      MDPORT.cb.lframe <= 1; // Start of frame
      for(int i = 0; i < 8; i++) begin // Send nibbles
        @(MDPORT.cb);
        MDPORT.cb.data <= req.data[3:0];
        req.data = req.data >> 4;
      end
      MDPORT.cb.lframe <= 0; // End of frame
      seq_item_port.item_done(); // Indicates that the sequence_item has been consumed
    end
  forever begin
    @(MDPORT.cb);
    if (MDPORT.cb.lframe === 1'b1) begin
      $display($time);
    end
  end
  join_none
endtask: run_phase

endclass: ac_lpc_driver

```

Thanks,

---

<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [November 21, 2017, 9:44am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/4 "2017-11-21T09:44:56Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/3):_

Two questions:  
(1) What is sequence\_item?  
(2) Is your driver connected to your sequencer in the Agent?

BTW you can skip the declaration of req.

---

<div class="post-metadata">

**Author:** ![ShivakumarAN](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/2acd7d/32.png) [@ShivakumarAN](https://verificationacademy.com/forums/u/ShivakumarAN)\
**Post date:** [November 21, 2017, 10:02am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/5 "2017-11-21T10:02:34Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/4):_

Hi Prawin,

You have declared seq\_item\_port as analysis port and trying to use built in methods of seq\_item\_port. Analysis port doesn’t have these methods and hence you are getting above error.  
You can remove the below line as seq\_item\_port is implicitly declared in uvm\_driver. Hope it helps.

uvm\_analysis\_port#(sequence\_item)seq\_item\_port;

–  
Regards,  
Shivakumar

---

<div class="post-metadata">

**Author:** ![santoshvaddisetty](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/a88e57/32.png) [@santoshvaddisetty](https://verificationacademy.com/forums/u/santoshvaddisetty)\
**Post date:** [November 21, 2017, 10:03am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/6 "2017-11-21T10:03:16Z")

</div>

Hi Prawin,

I will tell you what I understood from your question. Correct me if I am wrong.

1. “sequence\_item” is a class extended from “uvm\_sequence\_item”.
2. You have written the “sequence\_item” class definition inside a file. That file should be included in a package so that it gets compiled. The inclusion order should be for example

```verilog
package my_pkg;
  `include "sequence_item.sv"
  ...
  ...
  `include "my_driver.sv"
endpackage

```

So, it’s the “sequence\_item” class gets compiled first & then, the driver gets compiled. Please try this & let me know if this works for you.

Thanks,  
Santosh

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 21, 2017, 11:00am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/7 "2017-11-21T11:00:53Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm-error/33733/6):_

Hi chr\_sue,

1. sequence\_item is class extends from uvm\_sequence\_item.
2. yes, am connected sequencer and driver in agent only

sequence\_item is “req” declaration  
sequence\_item req;

Thanks,

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 21, 2017, 11:04am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/8 "2017-11-21T11:04:48Z")

</div>

_In reply to [Shivakumar AN](https://verificationacademy.com/forums/t/uvm-error/33733/7):_

Hi Shivakumar AN,

Ok i’ll remove that, but you have any other method?  
because of port declaration mandatory right???

Thanks,

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 21, 2017, 11:10am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/9 "2017-11-21T11:10:39Z")

</div>

_In reply to [santosh vaddisetty](https://verificationacademy.com/forums/t/uvm-error/33733/8):_

Hi santosh vaddisetty,

yes santosh your correct ,am coded like that only but little bit change as follows

package my\_pkg;  
class sequenc\_item extends from uvm\_sequenc\_item  
…  
…  
endclass  
…  
…  
class ac\_lpc\_driver extend from uvm\_driver  
…  
…  
endclass  
endpackage

So can you tell me what wrong behind the code for that error.

Thanks,

---

<div class="post-metadata">

**Author:** ![ShivakumarAN](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/2acd7d/32.png) [@ShivakumarAN](https://verificationacademy.com/forums/u/ShivakumarAN)\
**Post date:** [November 21, 2017, 11:16am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/10 "2017-11-21T11:16:02Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/9):_

Hi Prawin,

seq\_item\_port is already declared in base class uvm\_driver which you are extending from. So no need to declare it again in your ac\_lpc\_driver class.  
Also you have declared it as analysis\_port which is causing the error. get\_next\_item is a built in method of seq\_item\_port and not of analysis\_port.

–  
Regards,  
Shivakumar

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 21, 2017, 11:24am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/11 "2017-11-21T11:24:28Z")

</div>

_In reply to [Shivakumar AN](https://verificationacademy.com/forums/t/uvm-error/33733/10):_

Hi Shivakumar AN,

Ok, i’ll try that,

Thanks,  
Prawin

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 21, 2017, 12:51pm UTC](https://verificationacademy.com/forums/t/uvm-error/33733/12 "2017-11-21T12:51:04Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/11):_

Hi Shivakumar,

it’s compiled now, but with fatal error shown below,

code: if (!uvm\_config\_db#(virtual ac\_lpc\_if)::get(this, “”, “vif”, vif)) begin  
`uvm\_fatal(“ac\_lpc\_agent”, “No virtual interface specified for this agent instance”)

Error: uvm\_test\_top.env.agent [ac\_lpc\_agent] No virtual interface specified for this agent instance

Thanks,

---

<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [November 21, 2017, 3:16pm UTC](https://verificationacademy.com/forums/t/uvm-error/33733/13 "2017-11-21T15:16:05Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/12):_

It seems there is no uvm\_config\_db set command from the toplevel module of your UVM testbench or you are limiting the access by specifying a wrong hierarchical Path in the set Command.

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 22, 2017, 4:41am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/14 "2017-11-22T04:41:27Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm-error/33733/13):_

Hi,

I’m not clear of your statement.

---

<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [November 22, 2017, 9:52am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/15 "2017-11-22T09:52:25Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/14):_

If you want to retrieve a value from the config\_db using the get command, you have to perform a set command to the config\_db, to make sure there is a corresponding value in the config\_db.  
For the virtual interface the set will be done in the toplevel module of your UVM testbench.

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 23, 2017, 5:50am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/16 "2017-11-23T05:50:10Z")

</div>

_In reply to [chr\_sue](https://verificationacademy.com/forums/t/uvm-error/33733/15):_  
Hi,  
Can you tell me why am getting this error?

```verilog
 function void build_phase(uvm_phase phase);
 env = ac_lpc_env::type_id::create("env", this);
    //test_seq = ac_lpc_tx_seq::type_id::create("test_seq",this);
    sequencer = ac_lpc_sequencer::type_id::create("test_seq",this);
    
    if(!uvm_config_db#(virtual ac_lpc_if)::get(this, "", "vif", vif)) begin
      `uvm_fatal("ac_lpc_test", "No virtual interface specified for this test instance")
    end 
    uvm_config_db#(virtual ac_lpc_if)::set( this, "env", "vif", vif);
  endfunction

```

ERROR: uvm\_test\_top [ac\_lpc\_test] No virtual interface specified for this test instance.

Thanks,

---

<div class="post-metadata">

**Author:** ![ShivakumarAN](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/2acd7d/32.png) [@ShivakumarAN](https://verificationacademy.com/forums/u/ShivakumarAN)\
**Post date:** [November 23, 2017, 7:29am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/17 "2017-11-23T07:29:55Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/16):_

Hi Prawin,

You are getting this error because for every uvm\_config\_db get, there must be a corresponding set from the higher hierarchy. Looks like you have missed to set this interface from your TB Top. Please check for similar set code in your TB top:

uvm\_config\_db #(virtual ac\_lpc\_if)::set (null, “\*”, “vif”, vif);

Also you can refer to some examples of set-get and complete UVM environment from below links. I would suggest you to go through these examples and videos.

- [http://www.chipverify.com/uvm/top-module](http://www.chipverify.com/uvm/top-module)
- [Simple but complete UVM example | Verification Academy](https://verificationacademy.com/forums/uvm/simple-complete-uvm-example)
- [Basic UVM | Universal Verification Methodology | Verification Academy](https://verificationacademy.com/courses/basic-uvm)
- [Advanced UVM | Universal Verification Methodology | Verification Academy](https://verificationacademy.com/courses/advanced-uvm)

–  
Regards,  
Shivakumar

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 23, 2017, 7:51am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/18 "2017-11-23T07:51:13Z")

</div>

_In reply to [Shivakumar AN](https://verificationacademy.com/forums/t/uvm-error/33733/17):_

Hi shiva,

I made it shiva but in driver am getting error again .

ERROR: uvm\_test\_top.env.driver [ac\_lpc\_driver] No virtual interface specified for this driver instance

Thanks,

---

<div class="post-metadata">

**Author:** ![ShivakumarAN](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/2acd7d/32.png) [@ShivakumarAN](https://verificationacademy.com/forums/u/ShivakumarAN)\
**Post date:** [November 23, 2017, 10:13am UTC](https://verificationacademy.com/forums/t/uvm-error/33733/19 "2017-11-23T10:13:50Z")

</div>

_In reply to [Prawin kumar](https://verificationacademy.com/forums/t/uvm-error/33733/18):_

Can you try after changing  
uvm\_config\_db#(virtual ac\_lpc\_if)::set( this, “env”, “vif”, vif);  
to  
uvm\_config\_db#(virtual ac\_lpc\_if)::set( this, “\*”, “vif”, vif);

Giving \* will make sure all the below hierarchy components can get from higher hierarchy.

Thanks,  
Shivakumar

---

<div class="post-metadata">

**Author:** ![Prawinkumar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/48db29/32.png) [@Prawinkumar](https://verificationacademy.com/forums/u/Prawinkumar)\
**Post date:** [November 23, 2017, 12:23pm UTC](https://verificationacademy.com/forums/t/uvm-error/33733/20 "2017-11-23T12:23:04Z")

</div>

_In reply to [Shivakumar AN](https://verificationacademy.com/forums/t/uvm-error/33733/19):_

Hi,

before error in ‘test’ hierarchy

Now at ‘env’.

ERROR; uvm\_test\_top.env [ac\_lpc\_env] No virtual interface specified for this env instance.

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