# Unexpected Xs in the result of addition of two logic signals

**URL:** <https://verificationacademy.com/forums/t/unexpected-xs-in-the-result-of-addition-of-two-logic-signals/40368>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, Arithmetic-expressions\
**Created:** [May 6, 2022, 1:31pm UTC](https://verificationacademy.com/forums/t/unexpected-xs-in-the-result-of-addition-of-two-logic-signals/40368 "2022-05-06T13:31:49Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![AMARDEEP\_R\_PALURU](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/7c8e57/32.png) [@AMARDEEP\_R\_PALURU](https://verificationacademy.com/forums/u/AMARDEEP_R_PALURU)\
**Post date:** [May 6, 2022, 1:31pm UTC](https://verificationacademy.com/forums/t/unexpected-xs-in-the-result-of-addition-of-two-logic-signals/40368/1 "2022-05-06T13:31:49Z")

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I have a code where two signals are added. Only top bits of the signals are X. Bottom bits are 0s. But the result has all Xs. I would expect the bottom bits to be 0s in the result.

```verilog

logic [3:0] a; // 4'bxx00
logic [3:0] b; // 4'bxx00
logic [4:0] c;

assign c = a + b; // Results in c = 4'xxxxx

```

I am trying to understand why the bottom 2 bits are x in the result

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [May 6, 2022, 3:55pm UTC](https://verificationacademy.com/forums/t/unexpected-xs-in-the-result-of-addition-of-two-logic-signals/40368/2 "2022-05-06T15:55:23Z")

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_In reply to [AMARDEEP R PALURU](https://verificationacademy.com/forums/t/unexpected-xs-in-the-result-of-addition-of-two-logic-signals/40368):_

Because Verilog is pessimistic with arithmetic operators. It implements addition using the host CPU’s arithmetic instructions which only support 2-state addition.