# TLM vs Analysis

**URL:** <https://verificationacademy.com/forums/t/tlm-vs-analysis/37568>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [May 11, 2020, 4:37am UTC](https://verificationacademy.com/forums/t/tlm-vs-analysis/37568 "2020-05-11T04:37:53Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![SaratChandra](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/a6a055/32.png) [@SaratChandra](https://verificationacademy.com/forums/u/SaratChandra)\
**Post date:** [May 11, 2020, 4:37am UTC](https://verificationacademy.com/forums/t/tlm-vs-analysis/37568/1 "2020-05-11T04:37:53Z")

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Why we use TLM Port connection for driver to sequencer, why not monitor to scoreboard if there is one to one connection. What is the main purpose of these two. I know that TLM Port is bidirectional because of req and rsp and analysis port is unidirectional because it has write method and this is one to many connections. But can any one tell exactly what is the main purpose not to use TLM port for monitor to scoreboard and not to use for Analysis port f–drv to seqr

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**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [May 11, 2020, 7:49am UTC](https://verificationacademy.com/forums/t/tlm-vs-analysis/37568/2 "2020-05-11T07:49:43Z")

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_In reply to [SaratK](https://verificationacademy.com/forums/t/tlm-vs-analysis/37568):_

Both einterfaces are TLM interfaces. The 1-to-1 interface between driver and sequencer is a blocking interface. The driver determines when he need a new seq\_item. The connection between the monitor and the scoreboard has to be non-blockin and we might connect more than 1 component. For this scenario we are using the analysis port approach. The analysis port has to be connected to an uvm\_anaylsis\_fifo to become non-blocking without loosing data. If we would use a blocking interface we might loose data. because the monitor do not stop the DUT.

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**Author:** ![SaratChandra](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/a6a055/32.png) [@SaratChandra](https://verificationacademy.com/forums/u/SaratChandra)\
**Post date:** [May 11, 2020, 8:32am UTC](https://verificationacademy.com/forums/t/tlm-vs-analysis/37568/3 "2020-05-11T08:32:59Z")

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_In reply to [chr\_sue](https://verificationacademy.com/forums/t/tlm-vs-analysis/37568/2):_

Thank you chr\_sue. Perfect explanation.