# Systemverilog assertion what is the difference between "A throughout B" and "B throughout A"? **URL:** \ **Category:** SystemVerilog\ **Tags:** system-verilog-assertions-past-stable, SystemVerilog\ **Created:** [June 16, 2023, 5:48am UTC](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827 "2023-06-16T05:48:14Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![UVM\_LOVE](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/uvm_love/32/1684_2.png) [@UVM\_LOVE](https://verificationacademy.com/forums/u/UVM_LOVE)\ **Post date:** [June 16, 2023, 5:48am UTC](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/1 "2023-06-16T05:48:14Z")
Hi, A throughout B" is used to specify that property A holds continuously throughout the duration of property B. In other words, A is expected to be true for the entire time that B is true. This is the waveform [[Album] imgur.com ![](https://verificationacademy.com/forums/uploads/default/original/1X/8f48808533c6152719ff5a6b8b24a2316edfe34e.jpeg "imgur.com") ](https://imgur.com/a/uxoLXMA) I’m trying to make an assertion checker as the below, But “Busy[\*1:2] throughout DRdy” and “DRdy throughout Busy[\*1:2]” are working differently. why are CHK\_BPE1 and CHK\_BPE2 working differently? ```verilog property BPE1; @(posedge clk) (GntA) |=> DRdy throughout Busy[*1:2] ##0 Done; endproperty CHK_BPE1 : assert property (BPE1); ``` ```verilog property BPE2; 2 @(posedge clk) (GntA) |=> Busy[*1:2] throughout DRdy ##0 Done; endproperty CHK_BPE2 : assert property (BPE2); ``` ---
**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\ **Post date:** [June 16, 2023, 5:55am UTC](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/2 "2023-06-16T05:55:50Z")
_In reply to [UVM\_LOVE](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827):_ See my paper **Reflections on Users’ Experiences with SVA, part 2** [https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-e](https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-e) xperiences-with-sva-part-2 Addresses the usage of these four relationship operators: throughout, until, intersect, implies Ben Cohen [Ben@systemverilog.us](mailto:Ben@systemverilog.us) Link to the list of papers and books that I wrote, many are now donated. > **[Cohen\_Links\_to\_papers\_books.pdf](https://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf)** > > 141.16 KB or [Cohen\_Links\_to\_papers\_books - Google Docs](https://rb.gy/ibks5p) Getting started with verification with SystemVerilog > **[Ben Cohen on LinkedIn: Road map to start with verification: SV, SVA , UVM and TB](https://www.linkedin.com/posts/ben-cohen-1172a0_road-map-to-start-with-verification-sv-activity-7050267628208062464-wnzN?utm_source=share&utm_medium=member_desktop)** > > Got this question: > Q: I need your advice in getting started with verification with systemverilog. I 've built various projects using Verilog and they was… ---
**Author:** ![UVM\_LOVE](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/uvm_love/32/1684_2.png) [@UVM\_LOVE](https://verificationacademy.com/forums/u/UVM_LOVE)\ **Post date:** [June 16, 2023, 7:57am UTC](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/3 "2023-06-16T07:57:25Z")
_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/2):_ Hi ben, I understand the behavior of throughout. > **[Reflections on Users’ Experiences with SVA, Part II](https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-experiences-with-sva-part-2)** > > During my years of contributions to the Verification Academy SystemVerilog Forum, I have seen many trends in real users’ difficulties in the application of assertions, and misunderstandings of how SVA works. In Part 1 of this article, I addressed the... Thankfully… so I tried to another example. [[Album] imgur.com ![](https://verificationacademy.com/forums/uploads/default/original/1X/1971936f27a9989adbe9c05ad9eb1a162762cfcf.jpeg "imgur.com") ](https://imgur.com/a/pCcWlHE) ![](https://imgur.com/a/pCcWlHE) [Your text to link here…](https://imgur.com/a/pCcWlHE) property CHK02; @(posedge clk) $rose(idle) |=\> stable(!reset) throughout (idle [\*0:] ##1 !idle ##1 idle); endproperty CHK02\_P : assert property (CHK02); But this makes fail at 23NS. Could you give me a clue for resolve this? ---
**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\ **Post date:** [June 16, 2023, 3:30pm UTC](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/4 "2023-06-16T15:30:30Z")
_In reply to [UVM\_LOVE](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/3):_ SHould work per your waveform. The throughout operator specifies that a signal (expression) must hold throughout a sequence. ( b throughout R ) is equivalent to ( b [\*0:$] intersect R ) show your code ---
**Author:** ![UVM\_LOVE](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/uvm_love/32/1684_2.png) [@UVM\_LOVE](https://verificationacademy.com/forums/u/UVM_LOVE)\ **Post date:** [June 17, 2023, 5:18am UTC](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/5 "2023-06-17T05:18:55Z")
_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/4):_ sorry for late Ben. ```verilog module Testbench; // DUT signals logic clk; logic GntA=0; logic Busy=0; logic DRdy=0; logic Done=0; initial begin clk = 0; end // Instantiate assertion checkers initial begin // Initialize signals repeat(3) @(posedge clk); ///////////////////////////////////////////////////////////////// GntA = 1; repeat(1) @(posedge clk); GntA = 0; Busy = 1; DRdy = 1; repeat(1) @(posedge clk); Done =1; repeat(1) @(posedge clk); Done =0; Busy =0; DRdy = 0; repeat(14) @(posedge clk); // Finish simulation #100; $finish; end always #1 clk = ~clk; initial begin $shm_open("wave.shm"); $shm_probe("AS"); end property BPE1; @(posedge clk) (GntA) |=> Busy[*1:2] throughout DRdy ##0 Done; endproperty CHK_BPE1 : assert property (BPE1); property BPE2; @(posedge clk) (GntA) |=> DRdy throughout Busy[*1:2] ##0 Done; endproperty CHK_BPE2 : assert property (BPE2); endmodule ``` From BPE1, I get the error " Expected a verilog expression as operand to throughout operator." ---
**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\ **Post date:** [June 17, 2023, 6:50pm UTC](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/6 "2023-06-17T18:50:18Z")
_In reply to [UVM\_LOVE](https://verificationacademy.com/forums/t/systemverilog-assertion-what-is-the-difference-between-a-throughout-b-and-b-throughout-a/41827/5):_ You have to look at the syntax! 1800’2017 page 378 ```verilog sequence_expr ::= ... | sequence_expr intersect sequence_expr | sequence_expr or sequence_expr | first_match ( sequence_expr {, sequence_match_item} ) | expression_or_dist throughout sequence_expr // <<<<<<<<<<<< | sequence_expr within sequence_expr ``` The **throughout** requires an expression in the LHS you have (GntA) |=\> Busy[\*1:2] throughout DRdy ##0 Done; Busy[\*1:2] is a sequence