# System verilog : stable bus signal assertion

**URL:** <https://verificationacademy.com/forums/t/system-verilog-stable-bus-signal-assertion/37737>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, Assertion-system-verilog, assertion\
**Created:** [June 20, 2020, 12:01am UTC](https://verificationacademy.com/forums/t/system-verilog-stable-bus-signal-assertion/37737 "2020-06-20T00:01:42Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 20, 2020, 1:31am UTC](https://verificationacademy.com/forums/t/system-verilog-stable-bus-signal-assertion/37737/4 "2020-06-20T01:31:48Z")

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_In reply to [megamind](https://verificationacademy.com/forums/t/system-verilog-stable-bus-signal-assertion/37737/3):_  
Code looks complex and a bit misleading. Usually, $countones(v) is used when v is a vector greater than one bit. Of course, a one-bit vector is still a vector, but the goal of an assertion is to make things clearer. What you have makes my mind spin around trying to figure it out; a lot of mental gyrations. Why not write

```verilog

property p_value (i, v);
    if (v) (i==1'b1) else (i == 0); 
endproperty
// or even more simply 
property p_value (i, v);
    i==v; 
endproperty
// That looks more like a property of a D flip-flop. 
// We typically DO NOT WRITE Assertions FOR FLIP-FLOPS 
  ASRT_2 : assert property(@(posedge clk) disable iff (reset) p_value(single_bit_signal,0));

```

Ben Cohen  
[http://www.systemverilog.us/](http://www.systemverilog.us/) [ben@systemverilog.us](mailto:ben@systemverilog.us)  
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- [SVA Handbook 4th Edition, 2016 ISBN 978-1518681448](http://goo.gl/JOfuEB)
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- [Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712](https://goo.gl/d10QHh)
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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3. SVA in a UVM Class-based Environment  
[SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy](https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment)

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