# System Verilog Datatypes

**URL:** <https://verificationacademy.com/forums/t/system-verilog-datatypes/41718>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [May 29, 2023, 5:24am UTC](https://verificationacademy.com/forums/t/system-verilog-datatypes/41718 "2023-05-29T05:24:30Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Mechanic](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/9e8a1a/32.png) [@Mechanic](https://verificationacademy.com/forums/u/Mechanic)\
**Post date:** [May 29, 2023, 5:24am UTC](https://verificationacademy.com/forums/t/system-verilog-datatypes/41718/1 "2023-05-29T05:24:30Z")

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HI Team,

could you please provide one example why we don’t use **LOGIC** for bidirectional port **(INOUT)**?  
Why do we need to use **Wire**.? Please help

Regards,  
Sudarshan

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [May 30, 2023, 3:01pm UTC](https://verificationacademy.com/forums/t/system-verilog-datatypes/41718/2 "2023-05-30T15:01:06Z")

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_In reply to [Mechanic](https://verificationacademy.com/forums/t/system-verilog-datatypes/41718):_

An inout port requires multiple drivers on both sides to enable bidirectional data flow. Wires are the only kinds of signals that allow that. See [What's the deal with those wire’s and reg’s in Verilog - Verification Horizons](https://blogs.sw.siemens.com/verificationhorizons/2013/05/03/wire-vs-reg/)