System Verilog Assertion

at anyposedge of clk if A is asserted. In next cycle B should be asserted and it should be high continously till C is asserted. Once C is high it should be high for 4 to 5 clock cycles. The entire sequence should complete within 10 to 15 clock cycles.

sequence seq1;
     @(posedge clk)    
    ($rose(c) ##0 c[*4:5]); 
    endsequence   
  
  sequence seq2;
     @(posedge clk)    
    (b throughout !c[->1] ##[0:$] !b); 
    endsequence     
    
  sequence seq3;
     @(posedge clk)    
    ($rose(a) ##1 (seq1 and seq2)); 
    endsequence   
  
  assertion : assert property(
    @(posedge clk) disable iff(reset)    
    seq3 intersect 1[*10:15]);

My code is not working as per need. Can anyone help.
Thanks in advance.

Please format your code making your code easier for others to read. I have done that for you.

It would help to show a minimal, complete reproducible example

Thank you for sharing @dave_59. From my understanding I wrote 3 sequences that are correct or not, I don’t know that’s why I added them so other people will get the idea about my assertion.

@Vidhi

property p1;
  @(posedge clk) $rose(a) |=> ( ($rose(b) ##1 ( b throughout $rose(c)[->1] )) ##0 c[*4:5] ) intersect 1[*10:15] ;
endproperty

The assertion fails in following cases ::
(1) $rose(b) is false at the next clock after $rose(a) is true
(2) b isn’t high till C is asserted
(3) C isn’t asserted for 4 clocks
(4) LHS sequence of ‘intersect’ operator matches before 10 clocks