at anyposedge of clk if A is asserted. In next cycle B should be asserted and it should be high continously till C is asserted. Once C is high it should be high for 4 to 5 clock cycles. The entire sequence should complete within 10 to 15 clock cycles.
sequence seq1;
@(posedge clk)
($rose(c) ##0 c[*4:5]);
endsequence
sequence seq2;
@(posedge clk)
(b throughout !c[->1] ##[0:$] !b);
endsequence
sequence seq3;
@(posedge clk)
($rose(a) ##1 (seq1 and seq2));
endsequence
assertion : assert property(
@(posedge clk) disable iff(reset)
seq3 intersect 1[*10:15]);
My code is not working as per need. Can anyone help.
Thanks in advance.