Syntax error : System verilog keyword 'void' is not expected to b used in this context

OVM
8

The following code works fine for me:

class A;

static function void main();

string mode1[3] = '{“chip”, “boundary”, “chain”};
string mode2[2] = '{“chip”, “chain”};

print_it(mode1);
print_it(mode2);

endfunction: main

static function void print_it(string details);
foreach(details[i]) begin
$display(details[i]);
end
endfunction: print_it
endclass: A

module tb;

A a_h;

initial begin
a_h = new;
a_h.main();
end

endmodule: tb

I think the error message may be because you didn’t include the semi-colon at the end of the function header. Take care.