Syntax error : System verilog keyword 'void' is not expected to b used in this context

OVM
4

The problem is that you’re mixing up c syntax with SystemVerilog syntax.

The main function - do you really mean this given what the main function does in c? - should be implemented something along the lines of:

static function void main() string mode1[3] = '{"chip", "boundary", "chain"}; endfunction: main