# SVA signal stability check between 2 events

**URL:** <https://verificationacademy.com/forums/t/sva-signal-stability-check-between-2-events/31325>\
**Category:** SystemVerilog\
**Tags:** SVA, SystemVerilog\
**Created:** [December 17, 2015, 10:55am UTC](https://verificationacademy.com/forums/t/sva-signal-stability-check-between-2-events/31325 "2015-12-17T10:55:19Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![Lanfranco\_Salinari](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/l/5f8ce5/32.png) [@Lanfranco\_Salinari](https://verificationacademy.com/forums/u/Lanfranco_Salinari)\
**Post date:** [December 18, 2015, 9:13am UTC](https://verificationacademy.com/forums/t/sva-signal-stability-check-between-2-events/31325/3 "2015-12-18T09:13:35Z")

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_In reply to [lanfranco.salinari](https://verificationacademy.com/forums/t/sva-signal-stability-check-between-2-events/31325/2):_

Hello Ben,  
I, too, thought about a procedural solution in alternative to the SVA one.  
I don’t like very much the fact that I have to replicate the code for each signal (a macro can help here) but it may be manageable.  
By the way, I don’t think that loc\_sig is necessary: if end\_ev occurs first, sig has not changed, in the other case, sig has certainly toggled.  
Besides this a “disable fork” at the end is necessary, in my opinion, to avoid giving errors every time sig changes.  
stable\_ev and not\_stable\_ev are simply events to pass information to the testbench.

```verilog

always begin
    	@(start_ev); 
    	fork 
            begin
    		@(end_ev);
                -> stable_ev;
            end
            begin    			
    		@(sig); 
    		-> not_stable_ev; 
            end
    	join_any 
        disable fork
end 

```

What do you think about this variation?  
Thanks and regards,

Lanfranco

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