# SV Assertion

**URL:** <https://verificationacademy.com/forums/t/sv-assertion/41764>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [June 5, 2023, 5:44pm UTC](https://verificationacademy.com/forums/t/sv-assertion/41764 "2023-06-05T17:44:07Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![new\_to\_uvm](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/n/a6a055/32.png) [@new\_to\_uvm](https://verificationacademy.com/forums/u/new_to_uvm)\
**Post date:** [June 5, 2023, 5:44pm UTC](https://verificationacademy.com/forums/t/sv-assertion/41764/1 "2023-06-05T17:44:07Z")

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How do I write a property for the following:-  
When signal aa toggles from 0 to 1, signal bb should become 1’b0 after 5 ns and should remain 1’b0 till signal aa = 1.  
Note that signal aa is an asynchronous input.

Thanks!

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<div class="post-metadata">

**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 5, 2023, 9:04pm UTC](https://verificationacademy.com/forums/t/sv-assertion/41764/2 "2023-06-05T21:04:36Z")

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_In reply to [new\_to\_uvm](https://verificationacademy.com/forums/t/sv-assertion/41764):_  
Try something like the following:  
Keep in mind that task t\_aabb() is forked at every @(posedge aa), thus, the 2n posedge of aa will triggered it again.

with a guard for a single trigger of the task

> **[EDA Playground](https://www.edaplayground.com/x/HYHb)**
>
> Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

[(1) - EDA Playground](https://www.edaplayground.com/x/EnKE) // code below

```verilog
fork // bb==0 
    begin @(posedge bb) bb_err: assert(0) else err3=1; end // occurs before aa==1
    begin @(posedge aa) bb_ok: assert(! bb) else err4=1; end // bb should be 0 
  join_any 

```

```verilog

// When signal aa toggles from 0 to 1, signal bb should become 1'b0 after 5 ns 
// and should remain 1'b0 till signal aa = 1.
module m; 
  timeunit 100ps; timeprecision 100ps;    
  bit aa, bb, guard; 
  int err1, err2, err3, err4, done;

  task automatic t_aabb();
    realtime t; 
    t=$realtime;
    fork // bb==1 at entry 
    @(negedge bb) bb_early_ns: assert($realtime-t <50.1
                                      && $realtime-t >= 40.9) else err1=1; 
    #50.5 bb5ns: assert(bb==0) else err2=1;        
  join_any 
  fork // bb==0 
    begin @(posedge bb) bb_err: assert(0) else err3=1; end // occurs before aa==1
    begin @(posedge aa) bb_ok: assert(! bb) else err4=1; end // bb should be 0 
  join_any  
   done=done+1; // end of the task   
  endtask: t_aabb

  always @(posedge aa) if(!guard) fork t_aabb(); join_none 

  initial begin 
    $dumpfile("dump.vcd"); $dumpvars;
    repeat(1) begin 
     aa=0; bb=1; #20 aa=1; #10 aa=0; guard=1; #40 bb=0; #80 aa=1;
     #100 aa=0; bb=1; #20 aa=1; #10 aa=0; #70 bb=0; #80 aa=1;
     #20 $finish;
    end
  end 
endmodule 

```

Ben Cohen  
[Ben@systemverilog.us](mailto:Ben@systemverilog.us)  
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>
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or [Cohen\_Links\_to\_papers\_books - Google Docs](https://rb.gy/ibks5p)

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<div class="post-metadata">

**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 6, 2023, 10:11pm UTC](https://verificationacademy.com/forums/t/sv-assertion/41764/3 "2023-06-06T22:11:06Z")

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_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/sv-assertion/41764/2):_

I solved this assertion using the same approached I explained in my paper  
**Understanding the SVA Engine Using the Fork-Join Model** [Verification Horizons - July 2020 | Verification Academy](https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2) Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.

I strongly recommend reading this paper to understand the model behind SVA.