# Support back to back transactions in UVM driver

**URL:** <https://verificationacademy.com/forums/t/support-back-to-back-transactions-in-uvm-driver/37840>\
**Category:** UVM\
**Tags:** UVM, driver, back-to-back, b2b\
**Created:** [July 16, 2020, 4:13am UTC](https://verificationacademy.com/forums/t/support-back-to-back-transactions-in-uvm-driver/37840 "2020-07-16T04:13:42Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![shanthi](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/54ee81/32.png) [@shanthi](https://verificationacademy.com/forums/u/shanthi)\
**Post date:** [July 16, 2020, 4:43am UTC](https://verificationacademy.com/forums/t/support-back-to-back-transactions-in-uvm-driver/37840/2 "2020-07-16T04:43:33Z")

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_In reply to [AL\_verif](https://verificationacademy.com/forums/t/support-back-to-back-transactions-in-uvm-driver/37840):_  
You can control it from the sequence by giving the constraints and you can make the driver as reusable

```verilog

//sequence 

task body()
  req = item::type_id::create("req");
 // By Cange the loop limit you can control the no.of data to be driven continuously 
  repeat(10)
  begin
  start_item(req);
  assert(req.randomize() with{ valid == 1;});
  finish_item(req);
  end
  // After driving data making valid as 0
  start_item(req);
  assert(req.randomize() with{ valid == 0;});
  finish_item(req);
endtask

// Now in driver you need not to do any changes 
virtual task main_phase(uvm_phase phase);
   super.main_phase(phase);
 
   forever begin
      seq_item_port.get_next_item(req);
      drive_data(reg);
      seq_item_port.item_done();
   end
endtask : main_phase
 
 
// --------------------------------------
 
virtual protected task drive_data(item curr_item);
 
   // start transaction 
   @(posedge vif.clk);
   vif.valid <= 1;
   vif.data <= curr_item.data;
 

endtask:drive_data

```

Regards,  
Shanthi  
[www.maven-silicon.com](http://www.maven-silicon.com)

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