# Static vs Automatic

**URL:** <https://verificationacademy.com/forums/t/static-vs-automatic/40694>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, static-vs-automatic\
**Created:** [July 28, 2022, 8:20am UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694 "2022-07-28T08:20:03Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [July 28, 2022, 12:43pm UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694/2 "2022-07-28T12:43:54Z")

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_In reply to [mukul1996](https://verificationacademy.com/forums/t/static-vs-automatic/40694):_

Why would you expect the output to be 4,4 or 5,5? You are calling update() with a new value, which is updating the internal static value of ‘b’.

You have a race condition, so you could potentially have 4,5 or 5,4 but I’m not sure why you would expect something different.

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