# Static vs Automatic

**URL:** <https://verificationacademy.com/forums/t/static-vs-automatic/40694>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, static-vs-automatic\
**Created:** [July 28, 2022, 8:20am UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694 "2022-07-28T08:20:03Z")\
**Posts on this page:** 5\
**Page:** 1

<div class="post-metadata">

**Author:** ![mukul1996](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/ecb155/32.png) [@mukul1996](https://verificationacademy.com/forums/u/mukul1996)\
**Post date:** [July 28, 2022, 8:20am UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694/1 "2022-07-28T08:20:03Z")

</div>

```verilog

class a;
  static int b;
  static task update(int c = 0);
    b = c;
    $display("The value of b is = %0d", b);
   endtask
endclass

module check();
  a a1;

  initial begin
    a1 = new();
    fork
      begin
        #3 a1.update(4);
      end
      begin
       #3 a1.update(5);
      end
    join
  end
endmodule

```

The output is:  
The value of b is = 4  
The value of b is = 5

Why the output is not 4,4 or 5,5 as I am using static task as well as static property?

---

<div class="post-metadata">

**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [July 28, 2022, 12:43pm UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694/2 "2022-07-28T12:43:54Z")

</div>

_In reply to [mukul1996](https://verificationacademy.com/forums/t/static-vs-automatic/40694):_

Why would you expect the output to be 4,4 or 5,5? You are calling update() with a new value, which is updating the internal static value of ‘b’.

You have a race condition, so you could potentially have 4,5 or 5,4 but I’m not sure why you would expect something different.

---

<div class="post-metadata">

**Author:** ![mukul1996](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/ecb155/32.png) [@mukul1996](https://verificationacademy.com/forums/u/mukul1996)\
**Post date:** [July 28, 2022, 1:37pm UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694/3 "2022-07-28T13:37:10Z")

</div>

_In reply to [cgales](https://verificationacademy.com/forums/t/static-vs-automatic/40694/2):_

Hi,  
As “b” is declared as static, the memory for it would be allocated only one time at a fixed position.

So when at #3 we call update with different values, the last update which got executed should reflect the value.

---

<div class="post-metadata">

**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [July 28, 2022, 2:11pm UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694/4 "2022-07-28T14:11:18Z")

</div>

_In reply to [mukul1996](https://verificationacademy.com/forums/t/static-vs-automatic/40694/3):_

You are correct, in that the last update which got executed will be the final value.

However, when you call update, you also immediately call $display, so the value is updated with the argument that is passed in and then displayed. There is nothing blocking between the assignment and $display to allow any task switching.

A better example would decouple the update and display:

```verilog

class a;
  static int b;
  
  static function void print();
    $display("At time %0d The value of b is = %0d", $time, b);
  endfunction
  
  static function void update(int c = 0);
    b = c;
    print();
  endfunction
endclass
 
module check();
  a a1;
 
  initial begin
    a1 = new();
    fork
      begin
        #3 a1.update(4); // Update @time 3
        #1 a1.print(); // Display @time 4
        #3 a1.print(); // Display @time 7
      end
      begin
        #5 a1.update(5); // Update @time 5
        #1 a1.print(); // Display @time 6
      end
    join
  end
endmodule

```

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<div class="post-metadata">

**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [July 28, 2022, 3:12pm UTC](https://verificationacademy.com/forums/t/static-vs-automatic/40694/5 "2022-07-28T15:12:33Z")

</div>

_In reply to [cgales](https://verificationacademy.com/forums/t/static-vs-automatic/40694/4):_

Note the lifetimes of your tasks are still automatic. The static qualifier on a class method means the method can be called without constructing the class and may only access static class members. See [The life of a SystemVerilog variable](https://resources.sw.siemens.com/en-US/white-paper-the-life-of-a-systemverilog-variable)